2017-05-05 17:20:59 +01:00
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bpmp.h>
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#include <common/debug.h>
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#include <delay_timer.h>
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#include <errno.h>
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#include <mmio.h>
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#include <platform.h>
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#include <stdbool.h>
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#include <string.h>
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#include <tegra_def.h>
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#define BPMP_TIMEOUT_10US 10
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static uint32_t channel_base[NR_CHANNELS];
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static uint32_t bpmp_init_state = BPMP_INIT_PENDING;
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static uint32_t channel_field(unsigned int ch)
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{
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return mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET) & CH_MASK(ch);
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}
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static bool master_free(unsigned int ch)
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{
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return channel_field(ch) == MA_FREE(ch);
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}
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static bool master_acked(unsigned int ch)
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{
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return channel_field(ch) == MA_ACKD(ch);
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}
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static void signal_slave(unsigned int ch)
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{
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mmio_write_32(TEGRA_RES_SEMA_BASE + CLR_OFFSET, CH_MASK(ch));
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}
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static void free_master(unsigned int ch)
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{
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mmio_write_32(TEGRA_RES_SEMA_BASE + CLR_OFFSET,
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MA_ACKD(ch) ^ MA_FREE(ch));
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}
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/* should be called with local irqs disabled */
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int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
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void *ib_data, int ib_sz)
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{
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unsigned int ch = (unsigned int)plat_my_core_pos();
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mb_data_t *p = (mb_data_t *)(uintptr_t)channel_base[ch];
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int32_t ret = -ETIMEDOUT, timeout = 0;
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if (bpmp_init_state == BPMP_INIT_COMPLETE) {
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/* loop until BPMP is free */
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for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
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if (master_free(ch) == true) {
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break;
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}
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udelay(1);
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}
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if (timeout != BPMP_TIMEOUT_10US) {
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/* generate the command struct */
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p->code = mrq;
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p->flags = DO_ACK;
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(void)memcpy((void *)p->data, ob_data, (size_t)ob_sz);
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/* signal command ready to the BPMP */
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signal_slave(ch);
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mmio_write_32(TEGRA_PRI_ICTLR_BASE + CPU_IEP_FIR_SET,
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2017-07-26 10:16:54 +01:00
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(1U << INT_SHR_SEM_OUTBOX_FULL));
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2017-05-05 17:20:59 +01:00
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/* loop until the command is executed */
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for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
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if (master_acked(ch) == true) {
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break;
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}
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udelay(1);
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}
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if (timeout != BPMP_TIMEOUT_10US) {
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/* get the command response */
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(void)memcpy(ib_data, (const void *)p->data,
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(size_t)ib_sz);
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/* return error code */
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ret = p->code;
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/* free this channel */
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free_master(ch);
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}
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}
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} else {
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/* return error code */
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ret = -EINVAL;
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}
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if (timeout == BPMP_TIMEOUT_10US) {
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ERROR("Timed out waiting for bpmp's response");
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}
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return ret;
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}
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int tegra_bpmp_init(void)
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{
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uint32_t val, base;
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unsigned int ch;
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int ret = 0;
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if (bpmp_init_state != BPMP_INIT_COMPLETE) {
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/* check if the bpmp processor is alive. */
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val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
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if (val != SIGN_OF_LIFE) {
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ERROR("BPMP precessor not available\n");
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ret = -ENOTSUP;
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}
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/* check if clock for the atomics block is enabled */
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_ENB_V);
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if ((val & CAR_ENABLE_ATOMICS) == 0) {
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ERROR("Clock to the atomics block is disabled\n");
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}
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/* check if the atomics block is out of reset */
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val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_CLR_V);
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2017-06-13 00:45:23 +01:00
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if ((val & CAR_ENABLE_ATOMICS) == CAR_ENABLE_ATOMICS) {
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2017-05-05 17:20:59 +01:00
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ERROR("Reset to the atomics block is asserted\n");
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}
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/* base address to get the result from Atomics */
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base = TEGRA_ATOMICS_BASE + RESULT0_REG_OFFSET;
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/* channel area is setup by BPMP before signaling handshake */
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for (ch = 0; ch < NR_CHANNELS; ch++) {
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/* issue command to get the channel base address */
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mmio_write_32(base, (ch << TRIGGER_ID_SHIFT) |
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ATOMIC_CMD_GET);
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/* get the base address for the channel */
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channel_base[ch] = mmio_read_32(base);
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/* increment result register offset */
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2017-07-26 10:16:54 +01:00
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base += 4U;
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2017-05-05 17:20:59 +01:00
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}
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/* mark state as "initialized" */
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if (ret == 0)
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bpmp_init_state = BPMP_INIT_COMPLETE;
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/* the channel values have to be visible across all cpus */
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flush_dcache_range((uint64_t)channel_base, sizeof(channel_base));
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flush_dcache_range((uint64_t)&bpmp_init_state,
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sizeof(bpmp_init_state));
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INFO("%s: done\n", __func__);
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}
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return ret;
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}
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