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arm-trusted-firmware/plat/nvidia/tegra/include/drivers/bpmp_ipc.h

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Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware This patch adds the driver to communicate with the BPMP firmware on Tegra SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/ disable requests, module resets among other things. MRQ is short for Message ReQuest. This is the general purpose, multi channel messaging protocol that is widely used to communicate with BPMP. This is further divided into a common high level protocol and a peer-specific low level protocol. The higher level protocol specifies the peer identification, channel definition and allocation, message structure, message semantics and message dispatch process whereas the lower level protocol defines actual message transfer implementation details. Currently, BPMP supports two lower level protocols - Token Mail Operations (TMO), IVC Mail Operations (IMO). This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM Communication) protocol which is a lockless, shared memory messaging queue management protocol. The IVC peer is expected to perform the following as part of establishing a connection with BPMP. 1. Initialize the channels with tegra_ivc_init() or its equivalent. 2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that BPMP is notified via the doorbell. 3. Poll until the channel connection is established [tegra_ivc_channel_notified() return 0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return non zero. The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In future, more hardware blocks would be supported. Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-09-25 21:27:45 +01:00
/*
Tegra: bpmp_ipc: support to enable/disable module clocks This patch adds support to the bpmp_ipc driver to allow clients to enable/disable clocks to hardware blocks. Currently, the API only supports SE devices. Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90 Signed-off-by: steven kao <skao@nvidia.com>
2018-01-03 03:07:00 +00:00
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Tegra: include: fix violations of MISRA Rule 21.1 This patch fixes the violations of Rule 21.1 from all the Tegra common header files. Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
2020-01-09 16:52:10 +00:00
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware This patch adds the driver to communicate with the BPMP firmware on Tegra SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/ disable requests, module resets among other things. MRQ is short for Message ReQuest. This is the general purpose, multi channel messaging protocol that is widely used to communicate with BPMP. This is further divided into a common high level protocol and a peer-specific low level protocol. The higher level protocol specifies the peer identification, channel definition and allocation, message structure, message semantics and message dispatch process whereas the lower level protocol defines actual message transfer implementation details. Currently, BPMP supports two lower level protocols - Token Mail Operations (TMO), IVC Mail Operations (IMO). This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM Communication) protocol which is a lockless, shared memory messaging queue management protocol. The IVC peer is expected to perform the following as part of establishing a connection with BPMP. 1. Initialize the channels with tegra_ivc_init() or its equivalent. 2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that BPMP is notified via the doorbell. 3. Poll until the channel connection is established [tegra_ivc_channel_notified() return 0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return non zero. The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In future, more hardware blocks would be supported. Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-09-25 21:27:45 +01:00
*
* SPDX-License-Identifier: BSD-3-Clause
*/
Tegra: include: fix violations of MISRA Rule 21.1 This patch fixes the violations of Rule 21.1 from all the Tegra common header files. Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
2020-01-09 16:52:10 +00:00
#ifndef BPMP_IPC_H
#define BPMP_IPC_H
Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware This patch adds the driver to communicate with the BPMP firmware on Tegra SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/ disable requests, module resets among other things. MRQ is short for Message ReQuest. This is the general purpose, multi channel messaging protocol that is widely used to communicate with BPMP. This is further divided into a common high level protocol and a peer-specific low level protocol. The higher level protocol specifies the peer identification, channel definition and allocation, message structure, message semantics and message dispatch process whereas the lower level protocol defines actual message transfer implementation details. Currently, BPMP supports two lower level protocols - Token Mail Operations (TMO), IVC Mail Operations (IMO). This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM Communication) protocol which is a lockless, shared memory messaging queue management protocol. The IVC peer is expected to perform the following as part of establishing a connection with BPMP. 1. Initialize the channels with tegra_ivc_init() or its equivalent. 2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that BPMP is notified via the doorbell. 3. Poll until the channel connection is established [tegra_ivc_channel_notified() return 0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return non zero. The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In future, more hardware blocks would be supported. Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-09-25 21:27:45 +01:00
Makefile: remove extra include paths in INCLUDES Now it is needed to use the full path of the common header files. Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-28 09:01:18 +00:00
#include <lib/utils_def.h>
Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware This patch adds the driver to communicate with the BPMP firmware on Tegra SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/ disable requests, module resets among other things. MRQ is short for Message ReQuest. This is the general purpose, multi channel messaging protocol that is widely used to communicate with BPMP. This is further divided into a common high level protocol and a peer-specific low level protocol. The higher level protocol specifies the peer identification, channel definition and allocation, message structure, message semantics and message dispatch process whereas the lower level protocol defines actual message transfer implementation details. Currently, BPMP supports two lower level protocols - Token Mail Operations (TMO), IVC Mail Operations (IMO). This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM Communication) protocol which is a lockless, shared memory messaging queue management protocol. The IVC peer is expected to perform the following as part of establishing a connection with BPMP. 1. Initialize the channels with tegra_ivc_init() or its equivalent. 2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that BPMP is notified via the doorbell. 3. Poll until the channel connection is established [tegra_ivc_channel_notified() return 0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return non zero. The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In future, more hardware blocks would be supported. Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-09-25 21:27:45 +01:00
#include <stdbool.h>
#include <stdint.h>
/**
* Currently supported reset identifiers
*/
#define TEGRA_RESET_ID_XUSB_PADCTL U(114)
#define TEGRA_RESET_ID_GPCDMA U(70)
/**
* Function to initialise the IPC with the bpmp
*/
int32_t tegra_bpmp_ipc_init(void);
/**
* Handler to reset a module
*/
int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id);
Tegra: bpmp_ipc: support to enable/disable module clocks This patch adds support to the bpmp_ipc driver to allow clients to enable/disable clocks to hardware blocks. Currently, the API only supports SE devices. Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90 Signed-off-by: steven kao <skao@nvidia.com>
2018-01-03 03:07:00 +00:00
/**
* Handler to enable clock to a module. Only SE device is
* supported for now.
*/
int tegra_bpmp_ipc_enable_clock(uint32_t clk_id);
/**
* Handler to disable clock to a module. Only SE device is
* supported for now.
*/
int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);
Tegra: include: fix violations of MISRA Rule 21.1 This patch fixes the violations of Rule 21.1 from all the Tegra common header files. Rule 21.1 "#define and #undef shall not be used on a reserved identifier or reserved macro name" Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
2020-01-09 16:52:10 +00:00
#endif /* BPMP_IPC_H */