2016-01-15 09:17:32 +00:00
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2016-01-15 09:17:32 +00:00
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*/
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2018-12-14 00:18:21 +00:00
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#include <platform_def.h>
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2016-01-15 09:17:32 +00:00
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#include <arch.h>
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#include <asm_macros.S>
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2018-12-14 00:18:21 +00:00
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#include <common/bl_common.h>
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2016-01-15 09:17:32 +00:00
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#include <cortex_a53.h>
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#include <cortex_a72.h>
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#include <plat_private.h>
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2016-07-16 04:16:51 +01:00
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#include <plat_pmu_macros.S>
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2016-01-15 09:17:32 +00:00
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.globl cpuson_entry_point
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.globl cpuson_flags
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.globl platform_cpu_warmboot
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.globl plat_secondary_cold_boot_setup
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.globl plat_report_exception
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2018-08-14 17:10:06 +01:00
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.globl plat_is_my_cpu_primary
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2016-01-15 09:17:32 +00:00
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.globl plat_my_core_pos
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.globl plat_reset_handler
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2017-06-20 01:05:30 +01:00
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.globl plat_panic_handler
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2016-01-15 09:17:32 +00:00
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/*
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* void plat_reset_handler(void);
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*
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* Determine the SOC type and call the appropriate reset
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* handler.
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*
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*/
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func plat_reset_handler
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2016-07-16 04:16:51 +01:00
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq handler_a72
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b handler_end
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handler_a72:
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/*
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* This handler does the following:
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* Set the L2 Data RAM latency for Cortex-A72.
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* Set the L2 Tag RAM latency to for Cortex-A72.
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*/
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2017-06-05 22:54:46 +01:00
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mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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2016-07-16 04:16:51 +01:00
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(0x1 << 5))
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2017-06-05 22:54:46 +01:00
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msr CORTEX_A72_L2CTLR_EL1, x0
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2016-07-16 04:16:51 +01:00
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isb
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handler_end:
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ret
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2016-01-15 09:17:32 +00:00
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endfunc plat_reset_handler
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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2016-07-16 04:16:51 +01:00
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add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
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2016-01-15 09:17:32 +00:00
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ret
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endfunc plat_my_core_pos
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/* --------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* rk3368 does not do cold boot for secondary CPU */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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2018-08-14 17:10:06 +01:00
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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2016-01-15 09:17:32 +00:00
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_RK_PRIMARY_CPU
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cset x0, eq
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ret
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2018-08-14 17:10:06 +01:00
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endfunc plat_is_my_cpu_primary
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2016-01-15 09:17:32 +00:00
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2017-06-20 01:05:30 +01:00
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/* --------------------------------------------------------------------
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* void plat_panic_handler(void)
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* Call system reset function on panic. Set up an emergency stack so we
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* can run C functions (it only needs to last for a few calls until we
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* reboot anyway).
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* --------------------------------------------------------------------
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*/
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func plat_panic_handler
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msr spsel, #0
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bl plat_set_my_stack
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b rockchip_soc_soft_reset
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endfunc plat_panic_handler
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2016-01-15 09:17:32 +00:00
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/* --------------------------------------------------------------------
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* void platform_cpu_warmboot (void);
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* cpus online or resume enterpoint
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* --------------------------------------------------------------------
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*/
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Add new alignment parameter to func assembler macro
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:
.align X
myfunction:
However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.
An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:
[...]
endfunc plat_crash_console_putc
.align 16
func platform_cpu_warmboot
[...]
This assembles into the following plat_helpers.o:
Sections:
Idx Name Size [...] Algn
9 .text.plat_crash_console_putc 00010000 [...] 2**16
10 .text.platform_cpu_warmboot 00000080 [...] 2**3
As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).
There's no real way to fix this with the existing func macro. Code like
func myfunc
.align X
happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.
Also fix up all existing instances of this dangerous antipattern.
Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-08-01 23:16:36 +01:00
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func platform_cpu_warmboot _align=16
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mrs x0, MPIDR_EL1
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2016-07-16 04:16:51 +01:00
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and x19, x0, #MPIDR_CPU_MASK
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and x20, x0, #MPIDR_CLUSTER_MASK
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mov x0, x20
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func_rockchip_clst_warmboot
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2016-01-15 09:17:32 +00:00
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/* --------------------------------------------------------------------
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* big cluster id is 1
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* big cores id is from 0-3, little cores id 4-7
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* --------------------------------------------------------------------
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*/
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2016-07-16 04:16:51 +01:00
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add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT
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2016-01-15 09:17:32 +00:00
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/* --------------------------------------------------------------------
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* get per cpuup flag
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* --------------------------------------------------------------------
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*/
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adr x4, cpuson_flags
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2016-07-16 04:16:51 +01:00
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add x4, x4, x21, lsl #2
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2016-01-15 09:17:32 +00:00
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ldr w1, [x4]
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/* --------------------------------------------------------------------
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* check cpuon reason
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* --------------------------------------------------------------------
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*/
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2016-07-16 04:16:51 +01:00
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cmp w1, PMU_CPU_AUTO_PWRDN
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2016-01-15 09:17:32 +00:00
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b.eq boot_entry
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2016-07-16 04:16:51 +01:00
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cmp w1, PMU_CPU_HOTPLUG
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2016-01-15 09:17:32 +00:00
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b.eq boot_entry
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/* --------------------------------------------------------------------
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* If the boot core cpuson_flags or cpuson_entry_point is not
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* expection. force the core into wfe.
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* --------------------------------------------------------------------
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*/
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wfe_loop:
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wfe
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b wfe_loop
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boot_entry:
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2016-07-16 04:16:51 +01:00
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str wzr, [x4]
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2016-04-10 07:11:07 +01:00
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/* --------------------------------------------------------------------
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* get per cpuup boot addr
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* --------------------------------------------------------------------
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*/
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adr x5, cpuson_entry_point
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2016-07-16 04:16:51 +01:00
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ldr x2, [x5, x21, lsl #3]
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2016-01-15 09:17:32 +00:00
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br x2
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endfunc platform_cpu_warmboot
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/* --------------------------------------------------------------------
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* Per-CPU Secure entry point - resume or power up
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* --------------------------------------------------------------------
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*/
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.section tzfw_coherent_mem, "a"
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.align 3
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cpuson_entry_point:
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.rept PLATFORM_CORE_COUNT
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.quad 0
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.endr
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cpuson_flags:
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.rept PLATFORM_CORE_COUNT
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2016-04-10 07:11:07 +01:00
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.word 0
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2016-01-15 09:17:32 +00:00
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.endr
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2016-07-16 04:16:51 +01:00
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rockchip_clst_warmboot_data
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