2016-10-11 02:36:00 +01:00
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2016-10-11 02:36:00 +01:00
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef ROCKCHIP_PLAT_LD_S
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#define ROCKCHIP_PLAT_LD_S
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2016-10-11 02:36:00 +01:00
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2018-12-14 00:18:21 +00:00
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#include <lib/xlat_tables/xlat_tables_defs.h>
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2017-11-15 11:45:35 +00:00
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2016-10-11 02:36:00 +01:00
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MEMORY {
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SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
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2017-05-04 09:02:45 +01:00
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PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
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2016-10-11 02:36:00 +01:00
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}
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SECTIONS
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{
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. = SRAM_BASE;
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2017-11-15 11:45:35 +00:00
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ASSERT(. == ALIGN(PAGE_SIZE),
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2016-10-11 02:36:00 +01:00
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"SRAM_BASE address is not aligned on a page boundary.")
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/*
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* The SRAM space allocation for RK3399
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* ----------------
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2016-10-12 01:10:12 +01:00
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* | m0 code bin
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* ----------------
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2016-10-11 02:36:00 +01:00
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* | sram text
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* ----------------
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* | sram data
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* ----------------
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*/
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2017-11-15 11:45:35 +00:00
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.incbin_sram : ALIGN(PAGE_SIZE) {
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2016-10-12 01:10:12 +01:00
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__sram_incbin_start = .;
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*(.sram.incbin)
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rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-05-16 09:40:46 +01:00
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__sram_incbin_real_end = .;
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2017-11-15 11:45:35 +00:00
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. = ALIGN(PAGE_SIZE);
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2016-10-12 01:10:12 +01:00
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__sram_incbin_end = .;
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} >SRAM
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rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-05-16 09:40:46 +01:00
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ASSERT((__sram_incbin_real_end - __sram_incbin_start) <=
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SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit")
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2016-10-12 01:10:12 +01:00
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2017-11-15 11:45:35 +00:00
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.text_sram : ALIGN(PAGE_SIZE) {
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2016-10-11 02:36:00 +01:00
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__bl31_sram_text_start = .;
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*(.sram.text)
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*(.sram.rodata)
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rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-05-16 09:40:46 +01:00
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__bl31_sram_text_real_end = .;
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2017-11-15 11:45:35 +00:00
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. = ALIGN(PAGE_SIZE);
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2016-10-11 02:36:00 +01:00
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__bl31_sram_text_end = .;
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} >SRAM
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rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-05-16 09:40:46 +01:00
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ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <=
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SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit")
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2016-10-11 02:36:00 +01:00
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2017-11-15 11:45:35 +00:00
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.data_sram : ALIGN(PAGE_SIZE) {
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2016-10-11 02:36:00 +01:00
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__bl31_sram_data_start = .;
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*(.sram.data)
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rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-05-16 09:40:46 +01:00
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__bl31_sram_data_real_end = .;
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2017-11-15 11:45:35 +00:00
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. = ALIGN(PAGE_SIZE);
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2016-10-11 02:36:00 +01:00
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__bl31_sram_data_end = .;
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} >SRAM
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rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-05-16 09:40:46 +01:00
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ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <=
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SRAM_DATA_LIMIT, ".data_sram has exceeded its limit")
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2017-05-04 09:02:45 +01:00
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2017-11-15 11:45:35 +00:00
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.stack_sram : ALIGN(PAGE_SIZE) {
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2017-05-04 09:02:45 +01:00
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__bl31_sram_stack_start = .;
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2017-11-15 11:45:35 +00:00
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. += PAGE_SIZE;
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2017-05-04 09:02:45 +01:00
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__bl31_sram_stack_end = .;
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} >SRAM
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. = PMUSRAM_BASE;
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/*
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* pmu_cpuson_entrypoint request address
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* align 64K when resume, so put it in the
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* start of pmusram
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*/
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.pmusram : {
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ASSERT(. == ALIGN(64 * 1024),
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".pmusram.entry request 64K aligned.");
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*(.pmusram.entry)
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2018-04-20 08:55:21 +01:00
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2017-05-04 09:02:45 +01:00
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__bl31_pmusram_text_start = .;
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*(.pmusram.text)
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*(.pmusram.rodata)
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__bl31_pmusram_text_end = .;
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2018-04-20 08:55:21 +01:00
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/* M0 start address request 4K align */
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. = ALIGN(4096);
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__pmusram_incbin_start = .;
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*(.pmusram.incbin)
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__pmusram_incbin_end = .;
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2017-05-04 09:02:45 +01:00
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__bl31_pmusram_data_start = .;
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*(.pmusram.data)
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__bl31_pmusram_data_end = .;
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} >PMUSRAM
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2016-10-11 02:36:00 +01:00
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}
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2018-11-08 10:20:19 +00:00
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#endif /* ROCKCHIP_PLAT_LD_S */
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