2020-11-18 16:46:32 +00:00
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/*
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2022-01-04 22:15:18 +00:00
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* Copyright (c) 2022, ARM Limited. All rights reserved.
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2020-11-18 16:46:32 +00:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2021-05-18 21:23:31 +01:00
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#ifndef CORTEX_A510_H
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#define CORTEX_A510_H
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2020-11-18 16:46:32 +00:00
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2021-05-18 21:23:31 +01:00
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#define CORTEX_A510_MIDR U(0x410FD460)
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2020-11-18 16:46:32 +00:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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2021-05-18 21:23:31 +01:00
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#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
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2022-01-07 23:12:31 +00:00
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
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2022-02-16 04:55:22 +00:00
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#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
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#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
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2020-11-18 16:46:32 +00:00
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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2021-05-18 21:23:31 +01:00
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#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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2020-11-18 16:46:32 +00:00
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2022-01-04 22:15:18 +00:00
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/*******************************************************************************
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* Complex auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
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2022-01-06 20:54:49 +00:00
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/*******************************************************************************
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* Auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
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2021-05-18 21:23:31 +01:00
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#endif /* CORTEX_A510_H */
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