2015-08-25 12:33:14 +01:00
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/*
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2018-08-16 16:52:57 +01:00
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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2018-08-09 23:11:23 +01:00
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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2015-08-25 12:33:14 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2015-08-25 12:33:14 +01:00
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*/
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2018-12-14 00:18:21 +00:00
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#include <string.h>
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2016-03-18 20:07:33 +00:00
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#include <arch_helpers.h>
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2018-12-14 00:18:21 +00:00
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#include <common/debug.h>
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#include <lib/mmio.h>
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2015-09-14 05:01:39 +01:00
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#include <mce.h>
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#include <tegra_def.h>
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2016-03-18 20:07:33 +00:00
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#include <tegra_private.h>
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2015-09-14 05:01:39 +01:00
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2017-03-21 07:50:09 +00:00
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#define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U
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#define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU
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2015-09-14 05:01:39 +01:00
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2017-03-21 07:50:09 +00:00
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#define CPU_RESET_MODE_AA64 1U
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2015-09-14 05:01:39 +01:00
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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2015-09-14 05:01:39 +01:00
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uint32_t addr_low, addr_high;
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INFO("Setting up secondary CPU boot\n");
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2017-10-25 19:52:07 +01:00
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/* TZDRAM base will be used as the "resume" address */
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2018-11-09 17:08:16 +00:00
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addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64;
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addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU);
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2015-09-14 05:01:39 +01:00
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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2017-10-23 11:22:09 +01:00
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
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2015-09-14 05:01:39 +01:00
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addr_low);
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2017-10-23 11:22:09 +01:00
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
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2015-09-14 05:01:39 +01:00
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addr_high);
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2015-08-25 12:33:14 +01:00
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}
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