Tegra: drivers: memctrl: move chip specific defines to tegra_def.h
This patch moves the chip specific memory controller driver defines to the appropriate tegra_def.h files, for future compatibility. Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -43,7 +43,7 @@
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#define GPU_RESET_BIT (1 << 24)
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/* Video Memory base and size (live values) */
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static uintptr_t video_mem_base;
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static uint64_t video_mem_base;
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static uint64_t video_mem_size;
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/*
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@ -85,7 +85,9 @@ void tegra_memctrl_setup(void)
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(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
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/* video memory carveout */
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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(uint32_t)(video_mem_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
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}
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@ -208,7 +210,8 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
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enable_mmu_el3(0);
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done:
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
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/* store new values */
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@ -60,14 +60,6 @@
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#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
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#define MC_SMMU_TRANSLATION_ENABLE (~0)
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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static inline uint32_t tegra_mc_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_BASE + off);
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@ -352,51 +352,6 @@ typedef struct mc_streamid_security_cfg {
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#endif /* __ASSEMBLY__ */
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/*******************************************************************************
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* TZDRAM carveout configuration registers
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******************************************************************************/
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
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/*******************************************************************************
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* Video Memory carveout configuration registers
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******************************************************************************/
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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/*******************************************************************************
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* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers
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******************************************************************************/
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#define MC_TZRAM_BASE_LO 0x2194
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#define TZRAM_BASE_LO_SHIFT 12
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#define TZRAM_BASE_LO_MASK 0xFFFFF
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#define MC_TZRAM_BASE_HI 0x2198
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#define TZRAM_BASE_HI_SHIFT 0
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#define TZRAM_BASE_HI_MASK 3
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#define MC_TZRAM_SIZE 0x219C
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#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
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#define MC_TZRAM_CARVEOUT_CFG 0x2190
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#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
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#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
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#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25)
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#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7)
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC
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/*******************************************************************************
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* Memory Controller Reset Control registers
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******************************************************************************/
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@ -104,6 +104,16 @@
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******************************************************************************/
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#define TEGRA_MC_BASE 0x70019000
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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@ -120,6 +120,45 @@
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#define TEGRA_MC_STREAMID_BASE 0x02C00000
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#define TEGRA_MC_BASE 0x02C10000
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
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#define MC_TZRAM_BASE_LO 0x2194
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#define TZRAM_BASE_LO_SHIFT 12
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#define TZRAM_BASE_LO_MASK 0xFFFFF
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#define MC_TZRAM_BASE_HI 0x2198
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#define TZRAM_BASE_HI_SHIFT 0
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#define TZRAM_BASE_HI_MASK 3
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#define MC_TZRAM_SIZE 0x219C
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#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
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#define MC_TZRAM_CARVEOUT_CFG 0x2190
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#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
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#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
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#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25)
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#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7)
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC
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/*******************************************************************************
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* Tegra UART Controller constants
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******************************************************************************/
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@ -129,6 +129,16 @@
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******************************************************************************/
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#define TEGRA_MC_BASE 0x70019000
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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