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Merge changes Ic1796898,I93bd392a into integration 

* changes:
  fix(errata): workaround for Cortex A78 AE erratum 2395408
  fix(errata): workaround for Cortex A78 AE erratum 2376748
This commit is contained in:
Joanna Farley 2022-03-29 00:21:37 +02:00 committed by TrustedFirmware Code Review
parent ad88c37080 3f4d81dfd2
commit 0263c968a7
5 changed files with 126 additions and 9 deletions
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20
docs/design/cpu-specific-build-macros.rst
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@ -298,13 +298,21 @@ For Cortex-A78, the following errata build flags are defined :
For Cortex-A78 AE, the following errata build flags are defined :
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78
AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
still open.
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
This erratum is still open.
- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78
AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
still open.
- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
erratum is still open.
- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
erratum is still open.
- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
erratum is still open.
For Neoverse N1, the following errata build flags are defined :

2
include/lib/cpus/aarch64/cortex_a78.h
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@ -35,8 +35,10 @@
#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)
#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.

9
include/lib/cpus/aarch64/cortex_a78_ae.h
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -21,4 +21,11 @@
#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1
#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0
#define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40
#endif /* CORTEX_A78_AE_H */

86
lib/cpus/aarch64/cortex_a78_ae.S
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -104,6 +104,78 @@ func check_errata_1951502
b cpu_rev_var_range
endfunc check_errata_1951502
/* --------------------------------------------------
* Errata Workaround for A78 AE Erratum 2376748.
* This applies to revisions r0p0 and r0p1 of A78 AE.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_ae_2376748_wa
/* Compare x0 against revisions r0p0 - r0p1 */
mov x17, x30
bl check_errata_2376748
cbz x0, 1f
/* -------------------------------------------------------
* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
* behave like PLD/PRFM LD and not cause invalidations to
* other PE caches. There might be a small performance
* degradation to this workaround for certain workloads
* that share data.
* -------------------------------------------------------
*/
mrs x0, CORTEX_A78_AE_ACTLR2_EL1
orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
msr CORTEX_A78_AE_ACTLR2_EL1, x0
isb
1:
ret x17
endfunc errata_a78_ae_2376748_wa
func check_errata_2376748
/* Applies to revisions r0p0 and r0p1. */
mov x1, #CPU_REV(0, 0)
mov x2, #CPU_REV(0, 1)
b cpu_rev_var_range
endfunc check_errata_2376748
/* --------------------------------------------------
* Errata Workaround for A78 AE Erratum 2395408.
* This applies to revisions r0p0 and r0p1 of A78 AE.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a78_ae_2395408_wa
/* Compare x0 against revisions r0p0 - r0p1 */
mov x17, x30
bl check_errata_2395408
cbz x0, 1f
/* --------------------------------------------------------
* Disable folding of demand requests into older prefetches
* with L2 miss requests outstanding by setting the
* CPUACTLR2_EL1[40] to 1.
* --------------------------------------------------------
*/
mrs x0, CORTEX_A78_AE_ACTLR2_EL1
orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
msr CORTEX_A78_AE_ACTLR2_EL1, x0
isb
1:
ret x17
endfunc errata_a78_ae_2395408_wa
func check_errata_2395408
/* Applies to revisions r0p0 and r0p1. */
mov x1, #CPU_REV(0, 0)
mov x2, #CPU_REV(0, 1)
b cpu_rev_var_range
endfunc check_errata_2395408
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@ -132,6 +204,16 @@ func cortex_a78_ae_reset_func
bl errata_a78_ae_1951502_wa
#endif
#if ERRATA_A78_AE_2376748
mov x0, x18
bl errata_a78_ae_2376748_wa
#endif
#if ERRATA_A78_AE_2395408
mov x0, x18
bl errata_a78_ae_2395408_wa
#endif
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@ -197,6 +279,8 @@ func cortex_a78_ae_errata_report
*/
report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408
report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
ldp x8, x30, [sp], #16

18
lib/cpus/cpu-ops.mk
View File

@ -1,6 +1,6 @@
#
# Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
# Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -341,6 +341,14 @@ ERRATA_A78_AE_1941500 ?=0
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_1951502 ?=0
# Flag to apply erratum 2376748 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_2376748 ?=0
# Flag to apply erratum 2395408 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_2395408 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=0
@ -838,6 +846,14 @@ $(eval $(call add_define,ERRATA_A78_AE_1941500))
$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
$(eval $(call add_define,ERRATA_A78_AE_1951502))
# Process ERRATA_A78_AE_2376748 flag
$(eval $(call assert_boolean,ERRATA_A78_AE_2376748))
$(eval $(call add_define,ERRATA_A78_AE_2376748))
# Process ERRATA_A78_AE_2395408 flag
$(eval $(call assert_boolean,ERRATA_A78_AE_2395408))
$(eval $(call add_define,ERRATA_A78_AE_2395408))
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))