feat(plat/rcar3): update DDR setting for R-Car D3
Update R-Car D3 DDR setting rev.0.02. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I3e3a202fbb0ff1f0f38a968ab5f8633604a46432
This commit is contained in:
Toshiyuki Ogasahara
Marek Vasut
parent
71f2239f53
commit
042d710d1d
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation.
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* Copyright (c) 2015-2021, Renesas Electronics Corporation.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -11,7 +11,11 @@
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#include "rcar_def.h"
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#include "../ddr_regs.h"
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#define RCAR_DDR_VERSION "rev.0.01"
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#define RCAR_DDR_VERSION "rev.0.02"
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/* Average periodic refresh interval[ns]. Support 3900,7800 */
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#define REFRESH_RATE 3900
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#if RCAR_LSI != RCAR_D3
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#error "Don't have DDR initialize routine."
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@ -44,7 +48,7 @@ static void init_ddr_d3_1866(void)
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mmio_write_32(DBSC_DBTR16, 0x09210507);
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mmio_write_32(DBSC_DBTR17, 0x040E0000);
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mmio_write_32(DBSC_DBTR18, 0x00000200);
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mmio_write_32(DBSC_DBTR19, 0x012B004B);
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mmio_write_32(DBSC_DBTR19, 0x0129004B);
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mmio_write_32(DBSC_DBTR20, 0x020000FB);
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mmio_write_32(DBSC_DBTR21, 0x00040004);
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mmio_write_32(DBSC_DBBL, 0x00000000);
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@ -54,8 +58,8 @@ static void init_ddr_d3_1866(void)
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mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
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mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
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mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
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mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
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mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
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mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
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mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
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mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
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mmio_write_32(DBSC_DBCMD, 0x01000001);
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@ -101,7 +105,9 @@ static void init_ddr_d3_1866(void)
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;
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
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mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89);
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mmio_write_32(DBSC_DBPDRGD_0,
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(uint32_t) (REFRESH_RATE * 928 / 125) - 400
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+ 0x0A300000);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
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mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
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@ -117,7 +123,11 @@ static void init_ddr_d3_1866(void)
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
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mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
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mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
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if (REFRESH_RATE > 3900) {
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mmio_write_32(DBSC_DBPDRGD_0, 0x00000020);
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} else {
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mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
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}
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mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
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mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
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@ -225,8 +235,10 @@ static void init_ddr_d3_1866(void)
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
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r2 = mmio_read_32(DBSC_DBPDRGD_0);
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
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mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
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r2 = mmio_read_32(DBSC_DBPDRGD_0);
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mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
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@ -296,8 +308,10 @@ static void init_ddr_d3_1866(void)
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mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
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mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
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mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
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mmio_write_32(DBSC_DBRFCNF1, 0x00080E23);
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mmio_write_32(DBSC_DBCALCNF,
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(uint32_t) (64000000 / REFRESH_RATE) + 0x01000000);
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mmio_write_32(DBSC_DBRFCNF1,
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(uint32_t) (REFRESH_RATE * 116 / 125) + 0x00080000);
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mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
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mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
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mmio_write_32(DBSC_DBRFEN, 0x00000001);
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@ -346,6 +360,19 @@ static void init_ddr_d3_1600(void)
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{
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uint32_t i, r2, r3, r5, r6, r7, r12;
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mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
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mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
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mmio_write_32(CPG_SRCR4, 0x20000000);
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mmio_write_32(0xE61500DC, 0xe2200000);
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while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
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;
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mmio_write_32(CPG_SRSTCLR4, 0x20000000);
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mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
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mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
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mmio_write_32(DBSC_DBKIND, 0x00000007);
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mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
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@ -363,14 +390,14 @@ static void init_ddr_d3_1600(void)
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mmio_write_32(DBSC_DBTR10, 0x0000000C);
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mmio_write_32(DBSC_DBTR11, 0x0000000A);
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mmio_write_32(DBSC_DBTR12, 0x00120012);
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mmio_write_32(DBSC_DBTR13, 0x000000D0);
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mmio_write_32(DBSC_DBTR13, 0x000000CE);
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mmio_write_32(DBSC_DBTR14, 0x00140005);
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mmio_write_32(DBSC_DBTR15, 0x00050004);
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mmio_write_32(DBSC_DBTR16, 0x071F0305);
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mmio_write_32(DBSC_DBTR17, 0x040C0000);
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mmio_write_32(DBSC_DBTR18, 0x00000200);
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mmio_write_32(DBSC_DBTR19, 0x01000040);
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mmio_write_32(DBSC_DBTR20, 0x020000D8);
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mmio_write_32(DBSC_DBTR20, 0x020000D6);
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mmio_write_32(DBSC_DBTR21, 0x00040004);
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mmio_write_32(DBSC_DBBL, 0x00000000);
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mmio_write_32(DBSC_DBODT0, 0x00000001);
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@ -379,8 +406,8 @@ static void init_ddr_d3_1600(void)
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mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
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mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
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mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
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mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
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mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
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mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
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mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
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mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
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mmio_write_32(DBSC_DBCMD, 0x01000001);
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@ -426,13 +453,14 @@ static void init_ddr_d3_1600(void)
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;
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
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mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0);
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mmio_write_32(DBSC_DBPDRGD_0,
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(uint32_t) (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
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mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
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mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
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mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
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mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
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mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
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@ -442,7 +470,11 @@ static void init_ddr_d3_1600(void)
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
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mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
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mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
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if (REFRESH_RATE > 3900) {
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mmio_write_32(DBSC_DBPDRGD_0, 0x00000018);
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} else {
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mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
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}
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mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
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mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
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mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
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@ -549,9 +581,11 @@ static void init_ddr_d3_1600(void)
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
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r2 = mmio_read_32(DBSC_DBPDRGD_0);
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
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mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
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r2 = mmio_read_32(DBSC_DBPDRGD_0);
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
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mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
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mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
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@ -620,8 +654,10 @@ static void init_ddr_d3_1600(void)
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mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
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mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
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mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
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mmio_write_32(DBSC_DBRFCNF1, 0x00080C30);
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mmio_write_32(DBSC_DBCALCNF,
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(uint32_t) (64000000 / REFRESH_RATE) + 0x01000000);
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mmio_write_32(DBSC_DBRFCNF1,
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(uint32_t) (REFRESH_RATE * 99 / 125) + 0x00080000);
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mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
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mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
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mmio_write_32(DBSC_DBRFEN, 0x00000001);
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@ -693,7 +729,7 @@ int32_t rcar_dram_init(void)
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ddr_mbps = 1600;
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}
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NOTICE("BL2: DDR%d\n", ddr_mbps);
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NOTICE("BL2: DDR%d(%s)\n", ddr_mbps, RCAR_DDR_VERSION);
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return 0;
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}
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