fix(plat/xilinx/versal): resolve misra R7.2
MISRA Violation: MISRA-C:2012 R.7.2 - A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Change-Id: Iaf6db75e42913ddceccb803426287d0c47d7f31d
This commit is contained in:
Abhyuday Godhasara
parent
bc2637e379
commit
0623dcea0f
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -18,9 +18,9 @@
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#define PLATFORM_STACK_SIZE 0x440
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#define PLATFORM_CORE_COUNT U(2)
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_PWR_LVL U(1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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/*******************************************************************************
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* BL31 specific defines.
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@ -31,8 +31,8 @@
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* little space for growth.
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*/
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#ifndef VERSAL_ATF_MEM_BASE
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# define BL31_BASE 0xfffe0000
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# define BL31_LIMIT 0xffffffff
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# define BL31_BASE U(0xfffe0000)
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# define BL31_LIMIT U(0xffffffff)
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#else
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# define BL31_BASE (VERSAL_ATF_MEM_BASE)
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# define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE - 1)
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@ -45,8 +45,8 @@
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* BL32 specific defines.
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******************************************************************************/
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#ifndef VERSAL_BL32_MEM_BASE
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# define BL32_BASE 0x60000000
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# define BL32_LIMIT 0x7fffffff
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# define BL32_BASE U(0x60000000)
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# define BL32_LIMIT U(0x7fffffff)
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#else
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# define BL32_BASE (VERSAL_BL32_MEM_BASE)
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# define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE - 1)
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@ -56,7 +56,7 @@
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* BL33 specific defines.
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******************************************************************************/
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#ifndef PRELOADED_BL33_BASE
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# define PLAT_ARM_NS_IMAGE_BASE 0x8000000
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# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
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#else
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# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
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#endif
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@ -81,8 +81,8 @@
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define PLAT_VERSAL_GICD_BASE 0xF9000000
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#define PLAT_VERSAL_GICR_BASE 0xF9080000
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#define PLAT_VERSAL_GICD_BASE U(0xF9000000)
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#define PLAT_VERSAL_GICR_BASE U(0xF9080000)
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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@ -91,7 +91,7 @@
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*/
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#define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER
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#define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER
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#define PLAT_VERSAL_IPI_IRQ 62
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#define PLAT_VERSAL_IPI_IRQ U(62)
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#define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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@ -127,18 +127,18 @@
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#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
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/* IPI registers and bitfields */
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#define IPI0_REG_BASE 0xFF330000
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#define IPI0_REG_BASE U(0xFF330000)
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#define IPI0_TRIG_BIT (1 << 2)
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#define PMC_IPI_TRIG_BIT (1 << 1)
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#define IPI1_REG_BASE 0xFF340000
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#define IPI1_REG_BASE U(0xFF340000)
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#define IPI1_TRIG_BIT (1 << 3)
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#define IPI2_REG_BASE 0xFF350000
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#define IPI2_REG_BASE U(0xFF350000)
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#define IPI2_TRIG_BIT (1 << 4)
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#define IPI3_REG_BASE 0xFF360000
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#define IPI3_REG_BASE U(0xFF360000)
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#define IPI3_TRIG_BIT (1 << 5)
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#define IPI4_REG_BASE 0xFF370000
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#define IPI4_REG_BASE U(0xFF370000)
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#define IPI4_TRIG_BIT (1 << 5)
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#define IPI5_REG_BASE 0xFF380000
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#define IPI5_REG_BASE U(0xFF380000)
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#define IPI5_TRIG_BIT (1 << 6)
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#endif /* VERSAL_DEF_H */
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@ -21,7 +21,7 @@ static uintptr_t versal_sec_entry;
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static int versal_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
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int cpu_id = plat_core_pos_by_mpidr(mpidr);
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const struct pm_proc *proc;
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VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
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@ -30,10 +30,10 @@ static int versal_pwr_domain_on(u_register_t mpidr)
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return PSCI_E_INTERN_FAIL;
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}
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proc = pm_get_proc(cpu_id);
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proc = pm_get_proc((unsigned int)cpu_id);
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/* Send request to PMC to wake up selected ACPU core */
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pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1,
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pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
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versal_sec_entry >> 32, 0, SECURE_FLAG);
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/* Clear power down request */
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@ -54,7 +54,7 @@ static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
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unsigned int cpu_id = plat_my_core_pos();
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const struct pm_proc *proc = pm_get_proc(cpu_id);
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
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for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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}
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@ -91,7 +91,7 @@ static void versal_pwr_domain_suspend_finish(
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unsigned int cpu_id = plat_my_core_pos();
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const struct pm_proc *proc = pm_get_proc(cpu_id);
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
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for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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}
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@ -159,7 +159,7 @@ static void versal_pwr_domain_off(const psci_power_state_t *target_state)
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unsigned int cpu_id = plat_my_core_pos();
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const struct pm_proc *proc = pm_get_proc(cpu_id);
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for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
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for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
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VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
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__func__, i, target_state->pwr_domain_state[i]);
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -14,9 +14,9 @@
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#include "pm_svc_main.h"
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/* SMC function IDs for SiP Service queries */
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#define VERSAL_SIP_SVC_CALL_COUNT 0x8200ff00
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#define VERSAL_SIP_SVC_UID 0x8200ff01
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#define VERSAL_SIP_SVC_VERSION 0x8200ff03
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#define VERSAL_SIP_SVC_CALL_COUNT U(0x8200ff00)
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#define VERSAL_SIP_SVC_UID U(0x8200ff01)
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#define VERSAL_SIP_SVC_VERSION U(0x8200ff03)
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/* SiP Service Calls version numbers */
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#define SIP_SVC_VERSION_MAJOR 0
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -24,49 +24,49 @@ const static struct ipi_config versal_ipi_table[] = {
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[IPI_ID_APU] = {
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.ipi_bit_mask = IPI0_TRIG_BIT,
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.ipi_reg_base = IPI0_REG_BASE,
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.secure_only = 0,
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.secure_only = 0U,
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},
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/* PMC IPI */
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[IPI_ID_PMC] = {
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.ipi_bit_mask = PMC_IPI_TRIG_BIT,
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.ipi_reg_base = IPI0_REG_BASE,
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.secure_only = 0,
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.secure_only = 0U,
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},
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/* RPU0 IPI */
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[IPI_ID_RPU0] = {
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.ipi_bit_mask = IPI1_TRIG_BIT,
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.ipi_reg_base = IPI1_REG_BASE,
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.secure_only = 0,
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.secure_only = 0U,
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},
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/* RPU1 IPI */
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[IPI_ID_RPU1] = {
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.ipi_bit_mask = IPI2_TRIG_BIT,
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.ipi_reg_base = IPI2_REG_BASE,
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.secure_only = 0,
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.secure_only = 0U,
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},
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/* IPI3 IPI */
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[IPI_ID_3] = {
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.ipi_bit_mask = IPI3_TRIG_BIT,
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.ipi_reg_base = IPI3_REG_BASE,
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.secure_only = 0,
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.secure_only = 0U,
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},
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/* IPI4 IPI */
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[IPI_ID_4] = {
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.ipi_bit_mask = IPI4_TRIG_BIT,
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.ipi_reg_base = IPI4_REG_BASE,
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.secure_only = 0,
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.secure_only = 0U,
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},
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/* IPI5 IPI */
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[IPI_ID_5] = {
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.ipi_bit_mask = IPI5_TRIG_BIT,
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.ipi_reg_base = IPI5_REG_BASE,
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.secure_only = 0,
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.secure_only = 0U,
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},
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};
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