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Juno: Disable SPIDEN in release builds 

On Juno, the secure privileged invasive debug authentication signal
(SPIDEN) is controlled by board SCC registers, which by default enable
SPIDEN.  Disable secure privileged external debug in release builds by
programming the appropriate Juno SoC registers.

Change-Id: I61045f09a47dc647bbe95e1b7a60e768f5499f49
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
This commit is contained in:
dp-arm 2017-02-08 12:16:42 +00:00
parent 85e93ba093
commit 09fad4989e
2 changed files with 26 additions and 1 deletions
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7
include/plat/arm/css/common/css_def.h
View File

@ -101,6 +101,13 @@
#define SSC_VERSION_DESIGNER_ID_MASK 0xff
#define SSC_VERSION_PART_NUM_MASK 0xfff
/* SSC debug configuration registers */
#define SSC_DBGCFG_SET 0x14
#define SSC_DBGCFG_CLR 0x18
#define SPIDEN_INT_CLR_SHIFT 6
#define SPIDEN_SEL_SET_SHIFT 7
#ifndef __ASSEMBLY__
/* SSC_VERSION related accessors */

20
plat/arm/board/juno/juno_security.c
View File

@ -59,17 +59,35 @@ static void css_init_nic400(void)
~0);
}
/*******************************************************************************
* Initialize debug configuration.
******************************************************************************/
static void init_debug_cfg(void)
{
#if !DEBUG
/* Set internal drive selection for SPIDEN. */
mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
1U << SPIDEN_SEL_SET_SHIFT);
/* Drive SPIDEN LOW to disable invasive debug of secure state. */
mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
1U << SPIDEN_INT_CLR_SHIFT);
#endif
}
/*******************************************************************************
* Initialize the secure environment.
******************************************************************************/
void plat_arm_security_setup(void)
{
/* Initialize debug configuration */
init_debug_cfg();
/* Initialize the TrustZone Controller */
arm_tzc400_setup();
/* Do ARM CSS internal NIC setup */
css_init_nic400();
/* Do ARM CSS SoC security setup */
soc_css_security_setup();
/* Initialize the SMMU SSD tables*/
/* Initialize the SMMU SSD tables */
init_mmu401();
}