Tegra194: Update t194_nvg.h to v6.7
This patch updates the t194_nvg.h header file received from the CPU team to v6.7. Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774 Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
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@ -7,6 +7,8 @@
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#ifndef T194_NVG_H
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#define T194_NVG_H
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#include <lib/utils_def.h>
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/**
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* t194_nvg.h - Header for the NVIDIA Generic interface (NVG).
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* Official documentation for this interface is included as part
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@ -20,7 +22,7 @@
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*/
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enum {
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TEGRA_NVG_VERSION_MAJOR = U(6),
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TEGRA_NVG_VERSION_MINOR = U(6)
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TEGRA_NVG_VERSION_MINOR = U(7)
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};
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typedef enum {
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@ -71,6 +73,9 @@ typedef enum {
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TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77),
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TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78),
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TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79),
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TEGRA_NVG_CHANNEL_RT_SAFE_MASK = U(80),
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TEGRA_NVG_CHANNEL_RT_WINDOW_US = U(81),
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TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US = U(82),
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TEGRA_NVG_CHANNEL_LAST_INDEX
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} tegra_nvg_channel_id_t;
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@ -153,7 +158,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_power_perf_channel_t {
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struct {
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uint32_t perf_per_watt : U(1);
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uint32_t reserved_31_1 : U(31);
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uint32_t reserved_63_32 : U(32);
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@ -162,7 +167,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_power_modes_channel_t {
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struct {
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uint32_t low_battery : U(1);
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uint32_t reserved_1_1 : U(1);
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uint32_t battery_save : U(1);
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@ -182,7 +187,7 @@ typedef union nvg_channel_1_data_u {
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typedef union {
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uint64_t flat;
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struct nvg_ccplex_cache_control_channel_t {
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struct {
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uint32_t gpu_ways : U(5);
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uint32_t reserved_7_5 : U(3);
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uint32_t gpu_only_ways : U(5);
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@ -203,7 +208,7 @@ typedef union nvg_channel_2_data_u {
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typedef union {
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uint64_t flat;
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struct nvg_wake_time_channel_t {
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struct {
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uint32_t wake_time : U(32);
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uint32_t reserved_63_32 : U(32);
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} bits;
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@ -211,7 +216,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_cstate_info_channel_t {
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struct {
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uint32_t cluster_state : U(3);
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uint32_t reserved_6_3 : U(4);
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uint32_t update_cluster : U(1);
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@ -242,7 +247,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_lower_bound_channel_t {
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struct {
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uint32_t crossover_value : U(32);
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uint32_t reserved_63_32 : U(32);
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} bits;
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@ -250,7 +255,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_cstate_stat_query_channel_t {
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struct {
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uint32_t unit_id : U(4);
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uint32_t reserved_15_4 : U(12);
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uint32_t stat_id : U(16);
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@ -260,7 +265,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_num_cores_channel_t {
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struct {
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uint32_t num_cores : U(4);
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uint32_t reserved_31_4 : U(28);
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uint32_t reserved_63_32 : U(32);
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@ -269,7 +274,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_unique_logical_id_channel_t {
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struct {
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uint32_t unique_core_id : U(3);
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uint32_t reserved_31_3 : U(29);
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uint32_t reserved_63_32 : U(32);
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@ -278,7 +283,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_logical_to_physical_mappings_channel_t {
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struct {
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uint32_t lcore0_pcore_id : U(4);
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uint32_t lcore1_pcore_id : U(4);
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uint32_t lcore2_pcore_id : U(4);
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@ -306,7 +311,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_is_sc7_allowed_channel_t {
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struct {
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uint32_t is_sc7_allowed : U(1);
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uint32_t reserved_31_1 : U(31);
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uint32_t reserved_63_32 : U(32);
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@ -315,7 +320,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_core_online_channel_t {
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struct {
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uint32_t core_id : U(4);
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uint32_t reserved_31_4 : U(28);
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uint32_t reserved_63_32 : U(32);
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@ -324,7 +329,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_cc3_control_channel_t {
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struct {
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uint32_t freq_req : U(9);
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uint32_t reserved_30_9 : U(22);
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uint32_t enable : U(1);
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@ -374,7 +379,7 @@ typedef enum {
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typedef union {
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uint64_t flat;
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struct nvg_update_ccplex_gsc_channel_t {
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struct {
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uint32_t gsc_enum : U(16);
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uint32_t reserved_31_16 : U(16);
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uint32_t reserved_63_32 : U(32);
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@ -411,7 +416,7 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_hsm_error_ctrl_channel_t {
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struct {
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uint32_t uncorr : U(1);
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uint32_t corr : U(1);
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uint32_t reserved_31_2 : U(30);
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