Tegra: enable processor retention and L2/CPUECTLR access
This patch enables the processor retention and L2/CPUECTLR read/write access from the NS world only for Cortex-A57 CPUs on the Tegra SoCs. Change-Id: I9941a67686ea149cb95d80716fa1d03645325445 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -35,6 +35,22 @@
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#include <cortex_a53.h>
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#include <cortex_a53.h>
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#include <tegra_def.h>
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#include <tegra_def.h>
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#define MIDR_PN_CORTEX_A57 0xD07
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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/* Global functions */
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/* Global functions */
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.globl plat_is_my_cpu_primary
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_my_core_pos
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@ -57,7 +73,18 @@
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*/
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*/
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.macro cpu_init_common
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.macro cpu_init_common
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#if ENABLE_L2_DYNAMIC_RETENTION
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/* ------------------------------------------------
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* We enable procesor retention and L2/CPUECTLR NS
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* access for A57 CPUs only.
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* ------------------------------------------------
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*/
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mrs x0, midr_el1
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mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
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and x0, x0, x1
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lsr x0, x0, #MIDR_PN_SHIFT
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cmp x0, #MIDR_PN_CORTEX_A57
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b.ne 1f
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/* ---------------------------
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/* ---------------------------
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* Enable processor retention
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* Enable processor retention
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* ---------------------------
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* ---------------------------
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@ -68,18 +95,14 @@
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orr x0, x0, x1
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orr x0, x0, x1
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msr L2ECTLR_EL1, x0
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msr L2ECTLR_EL1, x0
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isb
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isb
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#endif
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#if ENABLE_CPU_DYNAMIC_RETENTION
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mrs x0, CPUECTLR_EL1
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mrs x0, CPUECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
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mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
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bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
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bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
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orr x0, x0, x1
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orr x0, x0, x1
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msr CPUECTLR_EL1, x0
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msr CPUECTLR_EL1, x0
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isb
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isb
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#endif
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#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
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/* -------------------------------------------------------
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/* -------------------------------------------------------
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* -------------------------------------------------------
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* -------------------------------------------------------
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@ -88,13 +111,12 @@
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msr actlr_el3, x0
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msr actlr_el3, x0
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msr actlr_el2, x0
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msr actlr_el2, x0
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isb
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isb
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#endif
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/* --------------------------------
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/* --------------------------------
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* Enable the cycle count register
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* Enable the cycle count register
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* --------------------------------
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* --------------------------------
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*/
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*/
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mrs x0, pmcr_el0
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1: mrs x0, pmcr_el0
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ubfx x0, x0, #11, #5 // read PMCR.N field
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ubfx x0, x0, #11, #5 // read PMCR.N field
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mov x1, #1
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mov x1, #1
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lsl x0, x1, x0
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lsl x0, x1, x0
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@ -47,20 +47,6 @@
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******************************************************************************/
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******************************************************************************/
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#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
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#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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/*******************************************************************************
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/*******************************************************************************
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* GIC memory map
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* GIC memory map
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******************************************************************************/
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******************************************************************************/
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@ -37,15 +37,6 @@ $(eval $(call add_define,TZDRAM_BASE))
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ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1
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ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1
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$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
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$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
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ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
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$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
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ENABLE_L2_DYNAMIC_RETENTION := 1
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$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION))
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ENABLE_CPU_DYNAMIC_RETENTION := 1
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$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION))
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PLATFORM_CLUSTER_COUNT := 2
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PLATFORM_CLUSTER_COUNT := 2
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$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
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$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
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