Merge changes from topic "sm/fix_a76_errata" into integration
* changes: Workaround for cortex-A76 errata 1286807 Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
This commit is contained in:
commit
0cdbd023e1
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@ -217,6 +217,18 @@ For Cortex-A76, the following errata build flags are defined :
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- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
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- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
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CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
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CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
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- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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DSU Errata Workarounds
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DSU Errata Workarounds
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----------------------
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----------------------
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@ -87,12 +87,13 @@ static inline void _op ## _type(uint64_t v) \
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* TLB maintenance accessor prototypes
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* TLB maintenance accessor prototypes
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******************************************************************************/
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******************************************************************************/
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#if ERRATA_A57_813419
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#if ERRATA_A57_813419 || ERRATA_A76_1286807
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/*
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/*
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* Define function for TLBI instruction with type specifier that implements
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* Define function for TLBI instruction with type specifier that implements
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* the workaround for errata 813419 of Cortex-A57.
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* the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
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* Cortex-A76.
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*/
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*/
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#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\
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#define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
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static inline void tlbi ## _type(void) \
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static inline void tlbi ## _type(void) \
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{ \
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{ \
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__asm__("tlbi " #_type "\n" \
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__asm__("tlbi " #_type "\n" \
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@ -102,9 +103,10 @@ static inline void tlbi ## _type(void) \
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/*
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/*
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* Define function for TLBI instruction with register parameter that implements
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* Define function for TLBI instruction with register parameter that implements
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* the workaround for errata 813419 of Cortex-A57.
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* the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
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* Cortex-A76.
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*/
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*/
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#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \
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#define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
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static inline void tlbi ## _type(uint64_t v) \
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static inline void tlbi ## _type(uint64_t v) \
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{ \
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{ \
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__asm__("tlbi " #_type ", %0\n" \
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__asm__("tlbi " #_type ", %0\n" \
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@ -125,27 +127,51 @@ static inline void dc ## _name(uint64_t v) \
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}
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}
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#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
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#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
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#if ERRATA_A57_813419
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
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#if ERRATA_A57_813419
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
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DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
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DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
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#elif ERRATA_A76_1286807
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
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#else
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#else
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
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#endif
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DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
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#endif
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#if ERRATA_A57_813419
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
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#if ERRATA_A57_813419
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
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DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
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DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is)
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#elif ERRATA_A76_1286807
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
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#else
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
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#endif
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#endif
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@ -12,9 +12,9 @@
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/*
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/*
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* TLBI instruction with type specifier that implements the workaround for
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* TLBI instruction with type specifier that implements the workaround for
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* errata 813419 of Cortex-A57.
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* errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76.
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*/
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*/
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#if ERRATA_A57_813419
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#if ERRATA_A57_813419 || ERRATA_A76_1286807
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#define TLB_INVALIDATE(_type) \
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#define TLB_INVALIDATE(_type) \
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tlbi _type; \
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tlbi _type; \
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dsb ish; \
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dsb ish; \
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@ -19,6 +19,7 @@
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#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
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#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
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#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
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/*******************************************************************************
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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* CPU Auxiliary Control register specific definitions.
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@ -27,10 +28,17 @@
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#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
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#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
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#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
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#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
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#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
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#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
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/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
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/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
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#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
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#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
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@ -213,7 +213,7 @@ func errata_a76_1073348_wa
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isb
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isb
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1:
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1:
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ret x17
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ret x17
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endfunc errata_a76_1073348_wa
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endfunc errata_a76_1073348_wa
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func check_errata_1073348
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func check_errata_1073348
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mov x1, #0x10
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mov x1, #0x10
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@ -276,6 +276,117 @@ func check_errata_1220197
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b cpu_rev_var_ls
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b cpu_rev_var_ls
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endfunc check_errata_1220197
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endfunc check_errata_1220197
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/* --------------------------------------------------
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* Errata Workaround for Cortex A76 Errata #1257314.
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* This applies only to revision <= r3p0 of Cortex A76.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a76_1257314_wa
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/*
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* Compare x0 against revision r3p0
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*/
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mov x17, x30
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bl check_errata_1257314
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cbz x0, 1f
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mrs x1, CORTEX_A76_CPUACTLR3_EL1
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orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
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msr CORTEX_A76_CPUACTLR3_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a76_1257314_wa
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func check_errata_1257314
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mov x1, #0x30
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b cpu_rev_var_ls
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endfunc check_errata_1257314
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/* --------------------------------------------------
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* Errata Workaround for Cortex A76 Errata #1262888.
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* This applies only to revision <= r3p0 of Cortex A76.
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* Inputs:
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||||||
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a76_1262888_wa
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/*
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* Compare x0 against revision r3p0
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*/
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mov x17, x30
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bl check_errata_1262888
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cbz x0, 1f
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mrs x1, CORTEX_A76_CPUECTLR_EL1
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orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51
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msr CORTEX_A76_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a76_1262888_wa
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|
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func check_errata_1262888
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mov x1, #0x30
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b cpu_rev_var_ls
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endfunc check_errata_1262888
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||||||
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/* --------------------------------------------------
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||||||
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* Errata Workaround for Cortex A76 Errata #1275112
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* and Errata #1262606.
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|
* This applies only to revision <= r3p0 of Cortex A76.
|
||||||
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* Inputs:
|
||||||
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: x0-x17
|
||||||
|
* --------------------------------------------------
|
||||||
|
*/
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func errata_a76_1275112_1262606_wa
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/*
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||||||
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* Compare x0 against revision r3p0
|
||||||
|
*/
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mov x17, x30
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||||||
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/*
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||||||
|
* Since both errata #1275112 and #1262606 have the same check, we can
|
||||||
|
* invoke any one of them for the check here.
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||||||
|
*/
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bl check_errata_1275112
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cbz x0, 1f
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mrs x1, CORTEX_A76_CPUACTLR_EL1
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orr x1, x1, CORTEX_A76_CPUACTLR_EL1_BIT_13
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msr CORTEX_A76_CPUACTLR_EL1, x1
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|
isb
|
||||||
|
1:
|
||||||
|
ret x17
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||||||
|
endfunc errata_a76_1275112_1262606_wa
|
||||||
|
|
||||||
|
func check_errata_1262606
|
||||||
|
mov x1, #0x30
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_1262606
|
||||||
|
|
||||||
|
func check_errata_1275112
|
||||||
|
mov x1, #0x30
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_1275112
|
||||||
|
|
||||||
|
/* ---------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A76 Errata #1286807.
|
||||||
|
* This applies only to revision <= r3p0 of Cortex A76.
|
||||||
|
* Due to the nature of the errata it is applied unconditionally
|
||||||
|
* when built in, report it as applicable in this case
|
||||||
|
* ---------------------------------------------------
|
||||||
|
*/
|
||||||
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func check_errata_1286807
|
||||||
|
#if ERRATA_A76_1286807
|
||||||
|
mov x0, #ERRATA_APPLIES
|
||||||
|
ret
|
||||||
|
#else
|
||||||
|
mov x1, #0x30
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
#endif
|
||||||
|
endfunc check_errata_1286807
|
||||||
|
|
||||||
func check_errata_cve_2018_3639
|
func check_errata_cve_2018_3639
|
||||||
#if WORKAROUND_CVE_2018_3639
|
#if WORKAROUND_CVE_2018_3639
|
||||||
mov x0, #ERRATA_APPLIES
|
mov x0, #ERRATA_APPLIES
|
||||||
|
@ -318,6 +429,21 @@ func cortex_a76_reset_func
|
||||||
bl errata_a76_1220197_wa
|
bl errata_a76_1220197_wa
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A76_1257314
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a76_1257314_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A76_1262606 || ERRATA_A76_1275112
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a76_1275112_1262606_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A76_1262888
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a76_1262888_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
#if WORKAROUND_CVE_2018_3639
|
#if WORKAROUND_CVE_2018_3639
|
||||||
/* If the PE implements SSBS, we don't need the dynamic workaround */
|
/* If the PE implements SSBS, we don't need the dynamic workaround */
|
||||||
mrs x0, id_aa64pfr1_el1
|
mrs x0, id_aa64pfr1_el1
|
||||||
|
@ -393,6 +519,11 @@ func cortex_a76_errata_report
|
||||||
report_errata ERRATA_A76_1073348, cortex_a76, 1073348
|
report_errata ERRATA_A76_1073348, cortex_a76, 1073348
|
||||||
report_errata ERRATA_A76_1130799, cortex_a76, 1130799
|
report_errata ERRATA_A76_1130799, cortex_a76, 1130799
|
||||||
report_errata ERRATA_A76_1220197, cortex_a76, 1220197
|
report_errata ERRATA_A76_1220197, cortex_a76, 1220197
|
||||||
|
report_errata ERRATA_A76_1257314, cortex_a76, 1257314
|
||||||
|
report_errata ERRATA_A76_1262606, cortex_a76, 1262606
|
||||||
|
report_errata ERRATA_A76_1262888, cortex_a76, 1262888
|
||||||
|
report_errata ERRATA_A76_1275112, cortex_a76, 1275112
|
||||||
|
report_errata ERRATA_A76_1286807, cortex_a76, 1286807
|
||||||
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
|
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
|
||||||
report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
|
report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
|
||||||
report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
|
report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
|
||||||
|
|
|
@ -210,6 +210,26 @@ ERRATA_A76_1130799 ?=0
|
||||||
# only to revision <= r2p0 of the Cortex A76 cpu.
|
# only to revision <= r2p0 of the Cortex A76 cpu.
|
||||||
ERRATA_A76_1220197 ?=0
|
ERRATA_A76_1220197 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 1257314 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r3p0 of the Cortex A76 cpu.
|
||||||
|
ERRATA_A76_1257314 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 1262606 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r3p0 of the Cortex A76 cpu.
|
||||||
|
ERRATA_A76_1262606 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 1262888 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r3p0 of the Cortex A76 cpu.
|
||||||
|
ERRATA_A76_1262888 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 1275112 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r3p0 of the Cortex A76 cpu.
|
||||||
|
ERRATA_A76_1275112 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 1286807 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r3p0 of the Cortex A76 cpu.
|
||||||
|
ERRATA_A76_1286807 ?=0
|
||||||
|
|
||||||
# Flag to apply T32 CLREX workaround during reset. This erratum applies
|
# Flag to apply T32 CLREX workaround during reset. This erratum applies
|
||||||
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
|
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
|
||||||
ERRATA_N1_1043202 ?=1
|
ERRATA_N1_1043202 ?=1
|
||||||
|
@ -375,6 +395,26 @@ $(eval $(call add_define,ERRATA_A76_1130799))
|
||||||
$(eval $(call assert_boolean,ERRATA_A76_1220197))
|
$(eval $(call assert_boolean,ERRATA_A76_1220197))
|
||||||
$(eval $(call add_define,ERRATA_A76_1220197))
|
$(eval $(call add_define,ERRATA_A76_1220197))
|
||||||
|
|
||||||
|
# Process ERRATA_A76_1257314 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A76_1257314))
|
||||||
|
$(eval $(call add_define,ERRATA_A76_1257314))
|
||||||
|
|
||||||
|
# Process ERRATA_A76_1262606 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A76_1262606))
|
||||||
|
$(eval $(call add_define,ERRATA_A76_1262606))
|
||||||
|
|
||||||
|
# Process ERRATA_A76_1262888 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A76_1262888))
|
||||||
|
$(eval $(call add_define,ERRATA_A76_1262888))
|
||||||
|
|
||||||
|
# Process ERRATA_A76_1275112 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A76_1275112))
|
||||||
|
$(eval $(call add_define,ERRATA_A76_1275112))
|
||||||
|
|
||||||
|
# Process ERRATA_A76_1286807 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A76_1286807))
|
||||||
|
$(eval $(call add_define,ERRATA_A76_1286807))
|
||||||
|
|
||||||
# Process ERRATA_N1_1043202 flag
|
# Process ERRATA_N1_1043202 flag
|
||||||
$(eval $(call assert_boolean,ERRATA_N1_1043202))
|
$(eval $(call assert_boolean,ERRATA_N1_1043202))
|
||||||
$(eval $(call add_define,ERRATA_N1_1043202))
|
$(eval $(call add_define,ERRATA_N1_1043202))
|
||||||
|
|
Loading…
Reference in New Issue