plat/arm/common: add an additional platform power level
For platforms using multi-threaded CPUs, there can be upto four platform power domain levels. At present, there are three platform power domain levels that are defined for the CSS platforms. Define a fourth level 'ARM_PWR_LVL3' as well to provide support for an additional platform power domain level. Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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#define ARM_PWR_LVL0 MPIDR_AFFLVL0
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#define ARM_PWR_LVL1 MPIDR_AFFLVL1
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#define ARM_PWR_LVL2 MPIDR_AFFLVL2
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#define ARM_PWR_LVL3 MPIDR_AFFLVL3
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/*
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* Macros for local power states in ARM platforms encoded by State-ID field
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