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Tegra: allow individual SoCs to restore their settings 

This patch uses the Memory controller driver's handler to restore
its settings and moves the other chip specific code to their own
'pwr_domain_on_finish' handlers.

Change-Id: I3c9d23bdab9e2e3c05034ff6812cf941ccd7a75e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2016-03-03 13:28:10 -08:00
parent 9f1c5dd19b
commit 102e408793
5 changed files with 27 additions and 7 deletions
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8
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
View File

@ -89,6 +89,14 @@ void tegra_memctrl_setup(void)
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
}
/*
* Restore Memory Controller settings after "System Suspend"
*/
void tegra_memctrl_restore_settings(void)
{
tegra_memctrl_setup();
}
/*
* Secure the BL31 DRAM aperture.
*

10
plat/nvidia/tegra/common/tegra_pm.c
View File

@ -168,14 +168,10 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
PSTATE_ID_SOC_POWERDN) {
/*
* Lock scratch registers which hold the CPU vectors.
* Restore Memory Controller settings as it loses state
* during system suspend.
*/
tegra_pmc_lock_cpu_vectors();
/*
* SMMU configuration.
*/
tegra_memctrl_setup();
tegra_memctrl_restore_settings();
/*
* Security configuration to allow DRAM/device access.

1
plat/nvidia/tegra/include/drivers/memctrl.h
View File

@ -32,6 +32,7 @@
#define __MEMCTRL_H__
void tegra_memctrl_setup(void);
void tegra_memctrl_restore_settings(void);
void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);

10
plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
View File

@ -107,6 +107,16 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr)
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
/*
* Lock scratch registers which hold the CPU vectors
*/
tegra_pmc_lock_cpu_vectors();
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);

5
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
View File

@ -154,6 +154,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PLAT_SYS_SUSPEND_STATE_ID) {
/*
* Lock scratch registers which hold the CPU vectors
*/
tegra_pmc_lock_cpu_vectors();
/*
* Enable WRAP to INCR burst type conversions for
* incoming requests on the AXI slave ports.