Tegra: allow individual SoCs to restore their settings
This patch uses the Memory controller driver's handler to restore its settings and moves the other chip specific code to their own 'pwr_domain_on_finish' handlers. Change-Id: I3c9d23bdab9e2e3c05034ff6812cf941ccd7a75e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -89,6 +89,14 @@ void tegra_memctrl_setup(void)
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
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}
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}
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/*
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* Restore Memory Controller settings after "System Suspend"
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*/
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void tegra_memctrl_restore_settings(void)
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{
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tegra_memctrl_setup();
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}
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/*
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/*
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* Secure the BL31 DRAM aperture.
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* Secure the BL31 DRAM aperture.
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*
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*
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@ -168,14 +168,10 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
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PSTATE_ID_SOC_POWERDN) {
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PSTATE_ID_SOC_POWERDN) {
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/*
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/*
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* Lock scratch registers which hold the CPU vectors.
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* Restore Memory Controller settings as it loses state
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* during system suspend.
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*/
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*/
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tegra_pmc_lock_cpu_vectors();
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tegra_memctrl_restore_settings();
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/*
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* SMMU configuration.
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*/
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tegra_memctrl_setup();
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/*
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/*
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* Security configuration to allow DRAM/device access.
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* Security configuration to allow DRAM/device access.
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@ -32,6 +32,7 @@
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#define __MEMCTRL_H__
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#define __MEMCTRL_H__
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void tegra_memctrl_setup(void);
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void tegra_memctrl_setup(void);
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void tegra_memctrl_restore_settings(void);
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
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void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
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void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
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@ -107,6 +107,16 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr)
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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/*
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* Lock scratch registers which hold the CPU vectors
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*/
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tegra_pmc_lock_cpu_vectors();
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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{
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tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
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tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
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@ -154,6 +154,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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PLAT_SYS_SUSPEND_STATE_ID) {
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PLAT_SYS_SUSPEND_STATE_ID) {
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/*
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* Lock scratch registers which hold the CPU vectors
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*/
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tegra_pmc_lock_cpu_vectors();
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/*
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/*
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* Enable WRAP to INCR burst type conversions for
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* Enable WRAP to INCR burst type conversions for
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* incoming requests on the AXI slave ports.
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* incoming requests on the AXI slave ports.
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