zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node
Existing implementation does not allow to change the value of the DIV1 because DIV2 does not have SET_RATE_PARENT flag. This causes DIV1 value to be fixed and only value of DIV2 will be adjusted according to required clock rate. Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b
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@ -582,7 +582,8 @@ static struct pm_clock_node gem_ref_ungated_nodes[] = {
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.type = TYPE_DIV2,
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.type = TYPE_DIV2,
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.offset = 16,
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.offset = 16,
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.width = 6,
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.width = 6,
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.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
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.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC |
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CLK_SET_RATE_PARENT,
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.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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.mult = NA_MULT,
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.mult = NA_MULT,
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.div = NA_DIV,
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.div = NA_DIV,
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