FVP: make usage of Trusted DRAM optional at build time
This patch groups the current contents of the Trusted DRAM region at address 0x00_0600_0000 (entrypoint mailboxes and BL3-1 parameters) in a single shared memory area that may be allocated to Trusted SRAM (default) or Trusted DRAM at build time by setting the FVP_SHARED_DATA_LOCATION make variable. The size of this shared memory is 4096 bytes. The combination 'Shared data in Trusted SRAM + TSP in Trusted DRAM' is not currently supported due to restrictions in the maximum number of mmu tables that can be created. Documentation has been updated to reflect these changes. Fixes ARM-software/tf-issues#100 Change-Id: I26ff04d33ce4cacf8d770d1a1e24132b4fc53ff0
This commit is contained in:
Juan Castillo
parent
637ebd2eb9
commit
186c1d4b26
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@ -955,22 +955,95 @@ PROGBITS sections then the resulting binary file would contain a bunch of zero
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bytes at the location of this NOBITS section, making the image unnecessarily
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bigger. Smaller images allow faster loading from the FIP to the main memory.
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On FVP platforms, we use the Trusted ROM and Trusted SRAM to store the trusted
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firmware binaries.
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On FVP platforms, we use the Trusted ROM, Trusted SRAM and, optionally, Trusted
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DRAM to store the trusted firmware binaries and shared data.
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* A 4KB page of shared memory is used to store the entrypoint mailboxes
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and the parameters passed between bootloaders. The shared memory can be
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allocated either at the top of Trusted SRAM or at the base of Trusted
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DRAM at build time. When allocated in Trusted SRAM, the amount of Trusted
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SRAM available to load the bootloader images will be reduced by the size
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of the shared memory.
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* BL1 is originally sitting in the Trusted ROM at address `0x0`. Its
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read-write data are relocated at the top of the Trusted SRAM at runtime.
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If the shared memory is allocated in Trusted SRAM, the BL1 read-write data
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is relocated just below the shared memory.
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* BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS
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sections will overwrite BL1 R/W data.
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* BL2 is loaded below BL3-1.
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* The TSP is loaded as the BL3-2 image at the base of the Trusted SRAM. Its
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NOBITS sections are allowed to overlay BL2.
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* The TSP is loaded as the BL3-2 image at the base of either the Trusted
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SRAM or Trusted DRAM. When loaded into Trusted SRAM, its NOBITS sections
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are allowed to overlay BL2. When loaded into Trusted DRAM, an offset
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corresponding to the size of the shared memory is applied to avoid
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overlap.
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This memory layout is designed to give the BL3-2 image as much memory as
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possible. It is illustrated by the following diagram.
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possible when it is loaded into Trusted SRAM. Depending on the location of the
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shared memory page and the TSP, it will result in different memory maps,
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illustrated by the following diagrams.
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** Shared data & TSP in Trusted SRAM (default option): **
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Trusted SRAM
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0x04040000 +----------+
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| Shared |
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0x0403F000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-1 PROGBITS |
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|----------| ------------------
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| BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-2 PROGBITS |
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0x04000000 +----------+ ------------------
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Trusted ROM
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0x04000000 +----------+
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| BL1 (ro) |
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0x00000000 +----------+
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** Shared data & TSP in Trusted DRAM: **
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Trusted DRAM
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0x08000000 +----------+
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| |
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| BL3-2 |
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| |
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0x06001000 |----------|
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| Shared |
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0x06000000 +----------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-1 PROGBITS |
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|----------| ------------------
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| BL2 |
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|----------|
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| |
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0x04000000 +----------+
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Trusted ROM
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0x04000000 +----------+
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| BL1 (ro) |
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0x00000000 +----------+
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** Shared data in Trusted DRAM, TSP in Trusted SRAM: **
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Trusted DRAM
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0x08000000 +----------+
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| |
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| |
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| |
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0x06001000 |----------|
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| Shared |
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0x06000000 +----------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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@ -988,8 +1061,8 @@ possible. It is illustrated by the following diagram.
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| BL1 (ro) |
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0x00000000 +----------+
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The TSP image may be loaded in Trusted DRAM instead. This doesn't change the
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memory layout of the other boot loader images in Trusted SRAM.
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Loading the TSP image in Trusted DRAM doesn't change the memory layout of the
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other boot loader images in Trusted SRAM.
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Each bootloader stage image layout is described by its own linker script. The
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linker scripts export some symbols into the program symbol table. Their values
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@ -133,6 +133,8 @@ the build system doesn't track dependency for build options. Therefore, if any
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of the build options are changed from a previous build, a clean build must be
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performed.
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#### Common build options
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* `BL30`: Path to BL3-0 image in the host file system. This image is optional.
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If a BL3-0 image is present then this option must be passed for the `fip`
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target
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@ -192,6 +194,19 @@ performed.
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synchronous method) or 1 (BL3-2 is initialized using asynchronous method).
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Default is 0.
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#### FVP specific build options
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* `FVP_SHARED_DATA_LOCATION`: location of the shared memory page. Available
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options:
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- 'tsram' (default) : top of Trusted SRAM
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- 'tdram' : base of Trusted DRAM
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* `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options:
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- 'tsram' (default) : base of Trusted SRAM
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- 'tdram' : Trusted DRAM (above shared data)
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For a better understanding of FVP options, the FVP memory map is detailed in
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[Firmware Design].
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### Creating a Firmware Image Package
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@ -56,8 +56,8 @@ plat_config_t plat_config;
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t fvp_mmap[] = {
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{ FVP_TRUSTED_ROM_BASE, FVP_TRUSTED_ROM_BASE, FVP_TRUSTED_ROM_SIZE,
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MT_MEMORY | MT_RO | MT_SECURE },
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{ FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE },
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{ FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE },
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{ FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE,
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@ -140,7 +140,7 @@ warm_reset:
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* its safe to read it here with SO attributes
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* ---------------------------------------------
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*/
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ldr x10, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
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ldr x10, =MBOX_BASE
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bl platform_get_core_pos
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lsl x0, x0, #CACHE_WRITEBACK_SHIFT
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ldr x0, [x10, x0]
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@ -153,8 +153,8 @@ _panic: b _panic
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/* -----------------------------------------------------
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* void platform_mem_init (void);
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*
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* Zero out the mailbox registers in the TZDRAM. The
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* mmu is turned off right now and only the primary can
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* Zero out the mailbox registers in the shared memory.
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* The mmu is turned off right now and only the primary can
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* ever execute this code. Secondaries will read the
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* mailboxes using SO accesses. In short, BL31 will
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* update the mailboxes after mapping the tzdram as
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@ -163,7 +163,7 @@ _panic: b _panic
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* -----------------------------------------------------
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*/
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func platform_mem_init
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ldr x0, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
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ldr x0, =MBOX_BASE
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mov w1, #PLATFORM_CORE_COUNT
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loop:
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str xzr, [x0], #CACHE_WRITEBACK_GRANULE
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@ -72,6 +72,11 @@ static meminfo_t bl2_tzram_layout
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__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
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section("tzfw_coherent_mem")));
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/* Assert that BL3-1 parameters fit in shared memory */
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CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) <
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(FVP_SHARED_RAM_BASE + FVP_SHARED_RAM_SIZE),
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assert_bl31_params_do_not_fit_in_shared_memory);
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/*******************************************************************************
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* Reference to structures which holds the arguments which need to be passed
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* to BL31
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@ -97,14 +102,6 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl2_to_bl31_params_mem_t *bl31_params_mem;
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#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
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/*
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* Ensure that the secure DRAM memory used for passing BL31 arguments
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* does not overlap with the BL32_BASE.
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*/
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assert(BL32_BASE > PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t));
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#endif
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/*
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* Allocate the memory for all the arguments that needs to
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* be passed to BL31
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@ -74,10 +74,27 @@
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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#define MBOX_OFF 0x1000
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/* 4KB shared memory */
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#define FVP_SHARED_RAM_SIZE 0x1000
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/* Base address where parameters to BL31 are stored */
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#define PARAMS_BASE FVP_TRUSTED_DRAM_BASE
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/* Location of shared memory */
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#if (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_DRAM)
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/* Shared memory at the base of Trusted DRAM */
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# define FVP_SHARED_RAM_BASE FVP_TRUSTED_DRAM_BASE
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# define FVP_TRUSTED_SRAM_LIMIT (FVP_TRUSTED_SRAM_BASE \
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+ FVP_TRUSTED_SRAM_SIZE)
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#elif (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_SRAM)
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# if (FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM)
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# error "Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported"
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# endif
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/* Shared memory at the top of the Trusted SRAM */
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# define FVP_SHARED_RAM_BASE (FVP_TRUSTED_SRAM_BASE \
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+ FVP_TRUSTED_SRAM_SIZE \
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- FVP_SHARED_RAM_SIZE)
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# define FVP_TRUSTED_SRAM_LIMIT FVP_SHARED_RAM_BASE
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#else
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# error "Unsupported FVP_SHARED_DATA_LOCATION_ID value"
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#endif
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#define DRAM1_BASE 0x80000000ull
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#define DRAM1_SIZE 0x80000000ull
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@ -239,4 +256,15 @@
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#define FVP_NSAID_HDLCD0 2
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#define FVP_NSAID_CLCD 7
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/*******************************************************************************
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* Shared Data
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******************************************************************************/
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/* Entrypoint mailboxes */
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#define MBOX_BASE FVP_SHARED_RAM_BASE
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#define MBOX_SIZE 0x200
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/* Base address where parameters to BL31 are stored */
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#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
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#endif /* __FVP_DEF_H__ */
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@ -103,7 +103,7 @@ int fvp_affinst_on(unsigned long mpidr,
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} while (psysr & PSYSR_AFF_L0);
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE + MBOX_OFF);
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fvp_mboxes = (mailbox_t *)MBOX_BASE;
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fvp_mboxes[linear_id].value = sec_entrypoint;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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sizeof(unsigned long));
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@ -240,8 +240,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
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/* Program the jump address for the target cpu */
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE +
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MBOX_OFF);
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fvp_mboxes = (mailbox_t *)MBOX_BASE;
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fvp_mboxes[linear_id].value = sec_entrypoint;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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sizeof(unsigned long));
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@ -330,8 +329,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
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fvp_pwrc_clr_wen(mpidr);
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/* Zero the jump address in the mailbox for this cpu */
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fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE +
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MBOX_OFF);
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fvp_mboxes = (mailbox_t *)MBOX_BASE;
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes[linear_id].value = 0;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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@ -83,14 +83,12 @@
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#define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \
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+ FVP_TRUSTED_ROM_SIZE)
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/*
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* Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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* Put BL1 RW at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL1_RW_BASE is calculated using the current BL1 RW debug size plus
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* a little space for growth.
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*/
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#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE - \
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0x6000)
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#define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE)
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#define BL1_RW_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x6000)
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#define BL1_RW_LIMIT FVP_TRUSTED_SRAM_LIMIT
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/*******************************************************************************
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* BL2 specific defines.
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@ -106,15 +104,13 @@
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE - \
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0x1D000)
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#define BL31_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x1D000)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE + \
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FVP_TRUSTED_SRAM_SIZE)
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#define BL31_LIMIT FVP_TRUSTED_SRAM_LIMIT
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/*******************************************************************************
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* BL32 specific defines.
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@ -131,7 +127,8 @@
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#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
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# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
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# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
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# define BL32_BASE (FVP_TRUSTED_DRAM_BASE + 0x2000)
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# define BL32_BASE (FVP_TRUSTED_DRAM_BASE \
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+ FVP_SHARED_RAM_SIZE)
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# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
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#else
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# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
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@ -28,6 +28,17 @@
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Shared memory may be allocated at the top of Trusted SRAM (tsram) or at the
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# base of Trusted SRAM (tdram)
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FVP_SHARED_DATA_LOCATION := tsram
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ifeq (${FVP_SHARED_DATA_LOCATION}, tsram)
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FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_SRAM
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else ifeq (${FVP_SHARED_DATA_LOCATION}, tdram)
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FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_DRAM
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else
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$(error "Unsupported FVP_SHARED_DATA_LOCATION value")
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endif
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# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
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# Trusted SRAM is the default.
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FVP_TSP_RAM_LOCATION := tsram
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@ -39,7 +50,14 @@ else
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$(error "Unsupported FVP_TSP_RAM_LOCATION value")
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endif
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ifeq (${FVP_SHARED_DATA_LOCATION}, tsram)
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ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
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$(error Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported)
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endif
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endif
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# Process flags
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$(eval $(call add_define,FVP_SHARED_DATA_LOCATION_ID))
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$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
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PLAT_INCLUDES := -Iplat/fvp/include/
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