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Add barriers to handle Secure Timer interrupts correctly 

This patch adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.

Change-Id: Ie2f01f4f2e5c032ba61c7014d09ad86a3c5a0b97
This commit is contained in:
Achin Gupta 2014-06-17 16:59:13 +01:00
parent 8be9e39d9b
commit 196231425e
1 changed files with 6 additions and 1 deletions
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7
bl32/tsp/tsp_timer.c
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@ -68,9 +68,14 @@ void tsp_generic_timer_handler(void)
/* Ensure that the timer did assert the interrupt */
assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
/* Disable the timer and reprogram it */
/*
* Disable the timer and reprogram it. The barriers ensure that there is
* no reordering of instructions around the reprogramming code.
*/
isb();
write_cntps_ctl_el1(0);
tsp_generic_timer_start();
isb();
}
/*******************************************************************************