AArch32: Common changes needed for BL1/BL2
This patch adds common changes to support AArch32 state in BL1 and BL2. Following are the changes: * Added functions for disabling MMU from Secure state. * Added AArch32 specific SMC function. * Added semihosting support. * Added reporting of unhandled exceptions. * Added uniprocessor stack support. * Added `el3_entrypoint_common` macro that can be shared by BL1 and BL32 (SP_MIN) BL stages. The `el3_entrypoint_common` is similar to the AArch64 counterpart with the main difference in the assembly instructions and the registers that are relevant to AArch32 execution state. * Enabled `LOAD_IMAGE_V2` flag in Makefile for `ARCH=aarch32` and added check to make sure that platform has not overridden to disable it. Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
This commit is contained in:
Yatharth Kochar
parent
a8aa7fec1d
commit
1a0a3f0622
12
Makefile
12
Makefile
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@ -188,6 +188,10 @@ ifneq (${GENERATE_COT},0)
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FWU_FIP_DEPS += fwu_certificates
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endif
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# For AArch32, enable new version of image loading.
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ifeq (${ARCH},aarch32)
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LOAD_IMAGE_V2 := 1
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endif
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################################################################################
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# Toolchain
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@ -364,6 +368,14 @@ ifeq (${LOAD_IMAGE_V2},1)
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endif
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endif
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# For AArch32, LOAD_IMAGE_V2 must be enabled.
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ifeq (${ARCH},aarch32)
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ifeq (${LOAD_IMAGE_V2}, 0)
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$(error "For AArch32, LOAD_IMAGE_V2 must be enabled.")
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endif
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endif
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################################################################################
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# Process platform overrideable behaviour
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################################################################################
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@ -32,6 +32,7 @@
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#include <asm_macros.S>
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.globl do_panic
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.globl report_exception
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/***********************************************************
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* The common implementation of do_panic for all BL stages
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@ -40,3 +41,14 @@ func do_panic
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b plat_panic_handler
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endfunc do_panic
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/***********************************************************
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* This function is called from the vector table for
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* unhandled exceptions. It reads the current mode and
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* passes it to platform.
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***********************************************************/
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func report_exception
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mrs r0, cpsr
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and r0, #MODE32_MASK
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bl plat_report_exception
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bl plat_panic_handler
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endfunc report_exception
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@ -776,11 +776,15 @@ called in the following circumstances:
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The default implementation doesn't do anything, to avoid making assumptions
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about the way the platform displays its status information.
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This function receives the exception type as its argument. Possible values for
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exceptions types are listed in the [include/common/bl_common.h] header file.
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Note that these constants are not related to any architectural exception code;
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they are just an ARM Trusted Firmware convention.
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For AArch64, this function receives the exception type as its argument.
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Possible values for exceptions types are listed in the
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[include/common/bl_common.h] header file. Note that these constants are not
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related to any architectural exception code; they are just an ARM Trusted
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Firmware convention.
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For AArch32, this function receives the exception mode as its argument.
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Possible values for exception modes are listed in the
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[include/lib/aarch32/arch.h] header file.
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### Function : plat_reset_handler()
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@ -2234,6 +2238,7 @@ _Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._
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[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S
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[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c
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[include/common/bl_common.h]: ../include/common/bl_common.h
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[include/lib/aarch32/arch.h]: ../include/lib/aarch32/arch.h
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[include/plat/arm/common/arm_def.h]: ../include/plat/arm/common/arm_def.h
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[include/plat/common/common_def.h]: ../include/plat/common/common_def.h
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[include/plat/common/platform.h]: ../include/plat/common/platform.h
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@ -69,6 +69,16 @@
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lsl \reg, \reg, \tmp
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.endm
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/*
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* Declare the exception vector table, enforcing it is aligned on a
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* 32 byte boundary.
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*/
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.macro vector_base label
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.section .vectors, "ax"
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.align 5
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\label:
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.endm
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/*
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* This macro calculates the base address of the current CPU's multi
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* processor(MP) stack using the plat_my_core_pos() index, the name of
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@ -0,0 +1,278 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __EL3_COMMON_MACROS_S__
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#define __EL3_COMMON_MACROS_S__
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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/*
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* Helper macro to initialise EL3 registers we care about.
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*/
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.macro el3_arch_init_common _exception_vectors
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/* ---------------------------------------------------------------------
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* Enable the instruction cache and alignment checks
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* ---------------------------------------------------------------------
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*/
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ldr r1, =(SCTLR_RES1 | SCTLR_I_BIT | SCTLR_A_BIT)
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ldcopr r0, SCTLR
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orr r0, r0, r1
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stcopr r0, SCTLR
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isb
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/* ---------------------------------------------------------------------
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* Set the exception vectors (VBAR/MVBAR).
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* ---------------------------------------------------------------------
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*/
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ldr r0, =\_exception_vectors
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stcopr r0, VBAR
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stcopr r0, MVBAR
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isb
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/* -----------------------------------------------------
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* Enable the SIF bit to disable instruction fetches
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* from Non-secure memory.
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* -----------------------------------------------------
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*/
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ldcopr r0, SCR
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orr r0, r0, #SCR_SIF_BIT
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stcopr r0, SCR
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/* -----------------------------------------------------
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* Enable the Asynchronous data abort now that the
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* exception vectors have been setup.
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* -----------------------------------------------------
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*/
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cpsie a
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isb
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/* Enable access to Advanced SIMD registers */
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ldcopr r0, NSACR
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bic r0, r0, #NSASEDIS_BIT
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bic r0, r0, #NSTRCDIS_BIT
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orr r0, r0, #(NASCR_CP10_BIT | NASCR_CP11_BIT)
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stcopr r0, NSACR
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isb
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/*
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* Enable access to Advanced SIMD, Floating point and to the Trace
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* functionality as well.
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*/
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ldcopr r0, CPACR
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bic r0, r0, #ASEDIS_BIT
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bic r0, r0, #TRCDIS_BIT
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orr r0, r0, #CPACR_ENABLE_FP_ACCESS
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stcopr r0, CPACR
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isb
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vmrs r0, FPEXC
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orr r0, r0, #FPEXC_EN_BIT
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vmsr FPEXC, r0
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isb
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.endm
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/* -----------------------------------------------------------------------------
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* This is the super set of actions that need to be performed during a cold boot
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* or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN).
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*
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* This macro will always perform reset handling, architectural initialisations
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* and stack setup. The rest of the actions are optional because they might not
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* be needed, depending on the context in which this macro is called. This is
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* why this macro is parameterised ; each parameter allows to enable/disable
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* some actions.
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*
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* _set_endian:
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* Whether the macro needs to configure the endianness of data accesses.
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*
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* _warm_boot_mailbox:
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* Whether the macro needs to detect the type of boot (cold/warm). The
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* detection is based on the platform entrypoint address : if it is zero
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* then it is a cold boot, otherwise it is a warm boot. In the latter case,
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* this macro jumps on the platform entrypoint address.
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*
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* _secondary_cold_boot:
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* Whether the macro needs to identify the CPU that is calling it: primary
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* CPU or secondary CPU. The primary CPU will be allowed to carry on with
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* the platform initialisations, while the secondaries will be put in a
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* platform-specific state in the meantime.
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*
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* If the caller knows this macro will only be called by the primary CPU
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* then this parameter can be defined to 0 to skip this step.
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*
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* _init_memory:
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* Whether the macro needs to initialise the memory.
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*
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* _init_c_runtime:
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* Whether the macro needs to initialise the C runtime environment.
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*
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* _exception_vectors:
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* Address of the exception vectors to program in the VBAR_EL3 register.
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* -----------------------------------------------------------------------------
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*/
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.macro el3_entrypoint_common \
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_set_endian, _warm_boot_mailbox, _secondary_cold_boot, \
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_init_memory, _init_c_runtime, _exception_vectors
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/* Make sure we are in Secure Mode */
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#if ASM_ASSERTION
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ldcopr r0, SCR
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tst r0, #SCR_NS_BIT
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ASM_ASSERT(eq)
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#endif
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.if \_set_endian
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/* -------------------------------------------------------------
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* Set the CPU endianness before doing anything that might
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* involve memory reads or writes.
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* -------------------------------------------------------------
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*/
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ldcopr r0, SCTLR
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bic r0, r0, #SCTLR_EE_BIT
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stcopr r0, SCTLR
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isb
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.endif /* _set_endian */
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/* Switch to monitor mode */
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cps #MODE32_mon
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isb
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.if \_warm_boot_mailbox
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/* -------------------------------------------------------------
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* This code will be executed for both warm and cold resets.
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* Now is the time to distinguish between the two.
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* Query the platform entrypoint address and if it is not zero
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* then it means it is a warm boot so jump to this address.
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* -------------------------------------------------------------
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*/
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bl plat_get_my_entrypoint
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cmp r0, #0
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bxne r0
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.endif /* _warm_boot_mailbox */
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/* ---------------------------------------------------------------------
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* It is a cold boot.
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* Perform any processor specific actions upon reset e.g. cache, TLB
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* invalidations etc.
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* ---------------------------------------------------------------------
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*/
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bl reset_handler
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el3_arch_init_common \_exception_vectors
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.if \_secondary_cold_boot
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/* -------------------------------------------------------------
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* Check if this is a primary or secondary CPU cold boot.
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* The primary CPU will set up the platform while the
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* secondaries are placed in a platform-specific state until the
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* primary CPU performs the necessary actions to bring them out
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* of that state and allows entry into the OS.
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* -------------------------------------------------------------
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*/
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bl plat_is_my_cpu_primary
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cmp r0, #0
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bne do_primary_cold_boot
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/* This is a cold boot on a secondary CPU */
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bl plat_secondary_cold_boot_setup
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/* plat_secondary_cold_boot_setup() is not supposed to return */
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bl plat_panic_handler
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do_primary_cold_boot:
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.endif /* _secondary_cold_boot */
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/* ---------------------------------------------------------------------
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* Initialize memory now. Secondary CPU initialization won't get to this
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* point.
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* ---------------------------------------------------------------------
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*/
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.if \_init_memory
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bl platform_mem_init
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.endif /* _init_memory */
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/* ---------------------------------------------------------------------
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* Init C runtime environment:
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* - Zero-initialise the NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section (if any).
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* - Relocate the data section from ROM to RAM, if required.
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* ---------------------------------------------------------------------
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*/
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.if \_init_c_runtime
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#if IMAGE_BL32
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/* -----------------------------------------------------------------
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* Invalidate the RW memory used by the BL32 (SP_MIN) image. This
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* includes the data and NOBITS sections. This is done to
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* safeguard against possible corruption of this memory by
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* dirty cache lines in a system cache as a result of use by
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* an earlier boot loader stage.
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* -----------------------------------------------------------------
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*/
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ldr r0, =__RW_START__
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ldr r1, =__RW_END__
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sub r1, r1, r0
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bl inv_dcache_range
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#endif /* IMAGE_BL32 */
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ldr r0, =__BSS_START__
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ldr r1, =__BSS_SIZE__
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bl zeromem
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#if USE_COHERENT_MEM
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ldr r0, =__COHERENT_RAM_START__
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ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem
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#endif
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#if IMAGE_BL1
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/* -----------------------------------------------------
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* Copy data from ROM to RAM.
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* -----------------------------------------------------
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*/
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ldr r0, =__DATA_RAM_START__
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ldr r1, =__DATA_ROM_START__
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ldr r2, =__DATA_SIZE__
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bl memcpy
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#endif
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.endif /* _init_c_runtime */
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/* ---------------------------------------------------------------------
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* Allocate a stack whose memory will be marked as Normal-IS-WBWA when
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* the MMU is enabled. There is no risk of reading stale stack memory
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* after enabling the MMU as only the primary CPU is running at the
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* moment.
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* ---------------------------------------------------------------------
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*/
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bl plat_set_my_stack
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.endm
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#endif /* __EL3_COMMON_MACROS_S__ */
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@ -191,6 +191,7 @@
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/* NASCR definitions */
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#define NSASEDIS_BIT (1 << 15)
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#define NSTRCDIS_BIT (1 << 20)
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#define NASCR_CP11_BIT (1 << 11)
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#define NASCR_CP10_BIT (1 << 10)
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@ -187,6 +187,9 @@ void flush_dcache_range(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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void disable_mmu_secure(void);
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void disable_mmu_icache_secure(void);
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DEFINE_SYSOP_FUNC(wfi)
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DEFINE_SYSOP_FUNC(wfe)
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DEFINE_SYSOP_FUNC(sev)
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@ -196,6 +199,9 @@ DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
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DEFINE_SYSOP_FUNC(isb)
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void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3,
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uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
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DEFINE_SYSREG_RW_FUNCS(spsr)
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DEFINE_SYSREG_RW_FUNCS(cpsr)
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@ -289,4 +295,6 @@ DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
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#define read_cntpct_el0() read64_cntpct()
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#define read_ctr_el0() read_ctr()
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#endif /* __ARCH_HELPERS_H__ */
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@ -42,12 +42,16 @@
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CPU_MIDR: /* cpu_ops midr */
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.space 4
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/* Reset fn is needed during reset */
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#if IMAGE_BL1 || IMAGE_BL32
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CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 4
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#endif
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#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
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CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
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.space 4
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CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
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.space 4
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#endif
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CPU_OPS_SIZE = .
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/*
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@ -60,13 +64,17 @@ CPU_OPS_SIZE = .
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.align 2
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.type cpu_ops_\_name, %object
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.word \_midr
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#if IMAGE_BL1 || IMAGE_BL32
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.if \_noresetfunc
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.word 0
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.else
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.word \_name\()_reset_func
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.endif
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#endif
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#if IMAGE_BL32
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.word \_name\()_core_pwr_dwn
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.word \_name\()_cluster_pwr_dwn
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#endif
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.endm
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#endif /* __CPU_MACROS_S__ */
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@ -41,9 +41,13 @@
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/*
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* Platform binary types for linking
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*/
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#ifdef AARCH32
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#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
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#define PLATFORM_LINKER_ARCH arm
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#else
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
#endif /* AARCH32 */
|
||||
|
||||
/*
|
||||
* Generic platform constants
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ uint32_t plat_interrupt_type_to_line(uint32_t type,
|
|||
* Optional common functions (may be overridden)
|
||||
******************************************************************************/
|
||||
uintptr_t plat_get_my_stack(void);
|
||||
void plat_report_exception(unsigned long);
|
||||
void plat_report_exception(unsigned int exception_type);
|
||||
int plat_crash_console_init(void);
|
||||
int plat_crash_console_putc(int c);
|
||||
void plat_error_handler(int err) __dead2;
|
||||
|
|
|
|||
|
|
@ -32,7 +32,21 @@
|
|||
#include <asm_macros.S>
|
||||
#include <assert_macros.S>
|
||||
|
||||
.globl smc
|
||||
.globl zeromem
|
||||
.globl disable_mmu_icache_secure
|
||||
.globl disable_mmu_secure
|
||||
|
||||
func smc
|
||||
/*
|
||||
* For AArch32 only r0-r3 will be in the registers;
|
||||
* rest r4-r6 will be pushed on to the stack. So here, we'll
|
||||
* have to load them from the stack to registers r4-r6 explicitly.
|
||||
* Clobbers: r4-r6
|
||||
*/
|
||||
ldm sp, {r4, r5, r6}
|
||||
smc #0
|
||||
endfunc smc
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
* void zeromem(void *mem, unsigned int length);
|
||||
|
|
@ -58,3 +72,25 @@ z_loop:
|
|||
z_end:
|
||||
bx lr
|
||||
endfunc zeromem
|
||||
|
||||
/* ---------------------------------------------------------------------------
|
||||
* Disable the MMU in Secure State
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
func disable_mmu_secure
|
||||
mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT)
|
||||
do_disable_mmu:
|
||||
ldcopr r0, SCTLR
|
||||
bic r0, r0, r1
|
||||
stcopr r0, SCTLR
|
||||
isb // ensure MMU is off
|
||||
dsb sy
|
||||
bx lr
|
||||
endfunc disable_mmu_secure
|
||||
|
||||
|
||||
func disable_mmu_icache_secure
|
||||
ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
|
||||
b do_disable_mmu
|
||||
endfunc disable_mmu_icache_secure
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#include <cpu_data.h>
|
||||
#include <cpu_macros.S>
|
||||
|
||||
#if IMAGE_BL1 || IMAGE_BL32
|
||||
/*
|
||||
* The reset handler common to all platforms. After a matching
|
||||
* cpu_ops structure entry is found, the correponding reset_handler
|
||||
|
|
@ -65,6 +66,9 @@ func reset_handler
|
|||
bx lr
|
||||
endfunc reset_handler
|
||||
|
||||
#endif /* IMAGE_BL1 || IMAGE_BL32 */
|
||||
|
||||
#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
|
||||
/*
|
||||
* The prepare core power down function for all platforms. After
|
||||
* the cpu_ops pointer is retrieved from cpu_data, the corresponding
|
||||
|
|
@ -132,6 +136,8 @@ func init_cpu_ops
|
|||
pop {r4 - r6, pc}
|
||||
endfunc init_cpu_ops
|
||||
|
||||
#endif /* IMAGE_BL32 */
|
||||
|
||||
/*
|
||||
* The below function returns the cpu_ops structure matching the
|
||||
* midr of the core. It reads the MIDR and finds the matching
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <asm_macros.S>
|
||||
|
||||
.globl semihosting_call
|
||||
|
||||
func semihosting_call
|
||||
svc #0x123456
|
||||
bx lr
|
||||
endfunc semihosting_call
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <asm_macros.S>
|
||||
#include <bl_common.h>
|
||||
#include <v2m_def.h>
|
||||
|
||||
.globl plat_report_exception
|
||||
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* void plat_report_exception(unsigned int type)
|
||||
* Function to report an unhandled exception
|
||||
* with platform-specific means.
|
||||
* On FVP platform, it updates the LEDs
|
||||
* to indicate where we are.
|
||||
* SYS_LED[0] - 0x0
|
||||
* SYS_LED[2:1] - 0x0
|
||||
* SYS_LED[7:3] - Exception Mode.
|
||||
* Clobbers: r0-r1
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
func plat_report_exception
|
||||
lsl r0, r0, #V2M_SYS_LED_EC_SHIFT
|
||||
ldr r1, =V2M_SYSREGS_BASE
|
||||
add r1, r1, #V2M_SYS_LED
|
||||
str r0, [r1]
|
||||
bx lr
|
||||
endfunc plat_report_exception
|
||||
|
|
@ -31,10 +31,8 @@
|
|||
PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ \
|
||||
-Iinclude/plat/arm/board/common/drivers
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S
|
||||
ifeq (${ARCH}, aarch64)
|
||||
PLAT_BL_COMMON_SOURCES += plat/arm/board/common/aarch64/board_arm_helpers.S
|
||||
endif
|
||||
PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S \
|
||||
plat/arm/board/common/${ARCH}/board_arm_helpers.S
|
||||
|
||||
BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c
|
||||
|
||||
|
|
|
|||
|
|
@ -34,9 +34,22 @@
|
|||
#include "../drivers/pwrc/fvp_pwrc.h"
|
||||
#include "../fvp_def.h"
|
||||
|
||||
.globl plat_secondary_cold_boot_setup
|
||||
.globl plat_get_my_entrypoint
|
||||
.globl plat_is_my_cpu_primary
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* void plat_secondary_cold_boot_setup (void);
|
||||
*
|
||||
* For AArch32, cold-booting secondary CPUs is not yet
|
||||
* implemented and they panic.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
func plat_secondary_cold_boot_setup
|
||||
cb_panic:
|
||||
b cb_panic
|
||||
endfunc plat_secondary_cold_boot_setup
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* unsigned long plat_get_my_entrypoint (void);
|
||||
*
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
|
||||
.weak plat_my_core_pos
|
||||
.weak plat_reset_handler
|
||||
.weak plat_disable_acp
|
||||
.weak platform_mem_init
|
||||
.weak plat_panic_handler
|
||||
|
||||
|
|
@ -59,6 +60,15 @@ func plat_reset_handler
|
|||
bx lr
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
* each platform.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_disable_acp
|
||||
bx lr
|
||||
endfunc plat_disable_acp
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
* each platform.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <platform_def.h>
|
||||
|
||||
.globl plat_get_my_stack
|
||||
.globl plat_set_my_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* unsigned long plat_get_my_stack ()
|
||||
*
|
||||
* For cold-boot BL images, only the primary CPU needs
|
||||
* a stack. This function returns the stack pointer for
|
||||
* a stack allocated in normal memory.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_get_my_stack
|
||||
get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE
|
||||
bx lr
|
||||
endfunc plat_get_my_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void plat_set_my_stack ()
|
||||
*
|
||||
* For cold-boot BL images, only the primary CPU needs
|
||||
* a stack. This function sets the stack pointer to a
|
||||
* stack allocated in normal memory.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_set_my_stack
|
||||
get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE
|
||||
mov sp, r0
|
||||
bx lr
|
||||
endfunc plat_set_my_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Per-cpu stacks in normal memory. Each cpu gets a
|
||||
* stack of PLATFORM_STACK_SIZE bytes.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
declare_stack platform_normal_stacks, tzfw_normal_stacks, \
|
||||
PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE
|
||||
Loading…
Reference in New Issue