Merge pull request #841 from dp-arm/dp/debug-regs

Disable secure self-hosted debug
This commit is contained in:
danh-arm 2017-02-20 13:58:48 +00:00 committed by GitHub
commit 1a80e88526
6 changed files with 52 additions and 3 deletions

View File

@ -98,6 +98,11 @@
orr r0, r0, #FPEXC_EN_BIT
vmsr FPEXC, r0
isb
/* Disable secure self-hosted invasive debug. */
ldr r0, =SDCR_DEF_VAL
stcopr r0, SDCR
.endm
/* -----------------------------------------------------------------------------

View File

@ -79,10 +79,11 @@
msr scr_el3, x0
/* ---------------------------------------------------------------------
* Reset registers that may have architecturally unknown reset values
* Disable secure self-hosted invasive debug.
* ---------------------------------------------------------------------
*/
msr mdcr_el3, xzr
mov_imm x0, MDCR_DEF_VAL
msr mdcr_el3, x0
/* ---------------------------------------------------------------------
* Enable External Aborts and SError Interrupts now that the exception

View File

@ -125,6 +125,14 @@
#define SCTLR_AFE_BIT (1 << 29)
#define SCTLR_TE_BIT (1 << 30)
/* SDCR definitions */
#define SDCR_SPD(x) ((x) << 14)
#define SDCR_SPD_LEGACY 0x0
#define SDCR_SPD_DISABLE 0x2
#define SDCR_SPD_ENABLE 0x3
#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
/* HSCTLR definitions */
#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \
| (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \
@ -345,6 +353,7 @@
/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
#define SCR p15, 0, c1, c1, 0
#define SCTLR p15, 0, c1, c0, 0
#define SDCR p15, 0, c1, c3, 1
#define MPIDR p15, 0, c0, c0, 5
#define MIDR p15, 0, c0, c0, 0
#define VBAR p15, 0, c12, c0, 0

View File

@ -195,6 +195,15 @@
#define SCR_NS_BIT (1 << 0)
#define SCR_VALID_BIT_MASK 0x2f8f
/* MDCR definitions */
#define MDCR_SPD32(x) ((x) << 14)
#define MDCR_SPD32_LEGACY 0x0
#define MDCR_SPD32_DISABLE 0x2
#define MDCR_SPD32_ENABLE 0x3
#define MDCR_SDD_BIT (1 << 16)
#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
/* HCR definitions */
#define HCR_RW_BIT (1ull << 31)
#define HCR_AMO_BIT (1 << 5)

View File

@ -101,6 +101,13 @@
#define SSC_VERSION_DESIGNER_ID_MASK 0xff
#define SSC_VERSION_PART_NUM_MASK 0xfff
/* SSC debug configuration registers */
#define SSC_DBGCFG_SET 0x14
#define SSC_DBGCFG_CLR 0x18
#define SPIDEN_INT_CLR_SHIFT 6
#define SPIDEN_SEL_SET_SHIFT 7
#ifndef __ASSEMBLY__
/* SSC_VERSION related accessors */

View File

@ -59,17 +59,35 @@ static void css_init_nic400(void)
~0);
}
/*******************************************************************************
* Initialize debug configuration.
******************************************************************************/
static void init_debug_cfg(void)
{
#if !DEBUG
/* Set internal drive selection for SPIDEN. */
mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
1U << SPIDEN_SEL_SET_SHIFT);
/* Drive SPIDEN LOW to disable invasive debug of secure state. */
mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
1U << SPIDEN_INT_CLR_SHIFT);
#endif
}
/*******************************************************************************
* Initialize the secure environment.
******************************************************************************/
void plat_arm_security_setup(void)
{
/* Initialize debug configuration */
init_debug_cfg();
/* Initialize the TrustZone Controller */
arm_tzc400_setup();
/* Do ARM CSS internal NIC setup */
css_init_nic400();
/* Do ARM CSS SoC security setup */
soc_css_security_setup();
/* Initialize the SMMU SSD tables*/
/* Initialize the SMMU SSD tables */
init_mmu401();
}