commit
1b05282abf
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@ -40,11 +40,11 @@
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_ACTLR p15, 0, c15
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#define CORTEX_A53_CPUACTLR p15, 0, c15
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#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT 44
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#define CORTEX_A53_ACTLR_ENDCCASCI (1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
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#define CORTEX_A53_ACTLR_DTAH (1 << 24)
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#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44
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#define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
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#define CORTEX_A53_CPUACTLR_DTAH (1 << 24)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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@ -67,4 +67,16 @@
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR p15, 3, c15
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A53_ACTLR CORTEX_A53_CPUACTLR
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#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
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#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_ENDCCASCI
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#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_DTAH
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A53_H__ */
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@ -6,6 +6,7 @@
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#ifndef __CORTEX_A57_H__
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#define __CORTEX_A57_H__
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#include <utils_def.h>
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/* Cortex-A57 midr for revision 0 */
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#define CORTEX_A57_MIDR 0x410FD070
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@ -24,13 +25,13 @@
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******************************************************************************/
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#define CORTEX_A57_ECTLR p15, 1, c15
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#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6)
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#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
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#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
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#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
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#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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@ -40,28 +41,28 @@
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_ACTLR p15, 0, c15
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#define CORTEX_A57_CPUACTLR p15, 0, c15
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#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59)
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#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
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#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52)
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#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49)
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#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44)
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#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38)
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#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27)
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#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25)
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#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
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#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
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#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
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#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2MERRSR p15, 3, c15
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR
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#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
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#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
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#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD
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#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
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#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI
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#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
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#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING
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#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
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#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A57_H__ */
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#ifndef __CORTEX_A72_H__
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#define __CORTEX_A72_H__
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#include <utils_def.h>
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/* Cortex-A72 midr for revision 0 */
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#define CORTEX_A72_MIDR 0x410FD080
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_ECTLR p15, 1, c15
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#define CORTEX_A72_ECTLR p15, 1, c15
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#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
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#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
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#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
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#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
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#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_MERRSR p15, 2, c15
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#define CORTEX_A72_MERRSR p15, 2, c15
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_ACTLR p15, 0, c15
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#define CORTEX_A72_CPUACTLR p15, 0, c15
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#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
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#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
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#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
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#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
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#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2MERRSR p15, 3, c15
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#define CORTEX_A72_L2MERRSR p15, 3, c15
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR
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#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
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#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
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#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_DCC_AS_DCCI
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A72_H__ */
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@ -22,53 +22,70 @@
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
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#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
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#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_ACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT U(44)
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#define CORTEX_A53_ACTLR_ENDCCASCI (U(1) << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
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#define CORTEX_A53_ACTLR_RADIS_SHIFT U(27)
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#define CORTEX_A53_ACTLR_RADIS (U(3) << CORTEX_A53_ACTLR_RADIS_SHIFT)
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#define CORTEX_A53_ACTLR_L1RADIS_SHIFT U(25)
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#define CORTEX_A53_ACTLR_L1RADIS (U(3) << CORTEX_A53_ACTLR_L1RADIS_SHIFT)
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#define CORTEX_A53_ACTLR_DTAH_SHIFT U(24)
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#define CORTEX_A53_ACTLR_DTAH (U(1) << CORTEX_A53_ACTLR_DTAH_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
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#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
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#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
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#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
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#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
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#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
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#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
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#if !ERROR_DEPRECATED
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/*
|
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* These registers were previously wrongly named. Provide previous definitions
|
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* so as not to break platforms that continue using them.
|
||||
*/
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#define CORTEX_A53_ACTLR_EL1 CORTEX_A53_CPUACTLR_EL1
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#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
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#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
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#define CORTEX_A53_ACTLR_RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
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#define CORTEX_A53_ACTLR_RADIS CORTEX_A53_CPUACTLR_EL1_RADIS
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#define CORTEX_A53_ACTLR_L1RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
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#define CORTEX_A53_ACTLR_L1RADIS CORTEX_A53_CPUACTLR_EL1_L1RADIS
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#define CORTEX_A53_ACTLR_DTAH_SHIFT CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
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#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_EL1_DTAH
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A53_H__ */
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||||
|
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
#ifndef __CORTEX_A57_H__
|
||||
#define __CORTEX_A57_H__
|
||||
#include <utils_def.h>
|
||||
|
||||
/* Cortex-A57 midr for revision 0 */
|
||||
#define CORTEX_A57_MIDR U(0x410FD070)
|
||||
|
@ -40,30 +41,30 @@
|
|||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0
|
||||
#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
|
||||
|
||||
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
|
||||
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
|
||||
#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52)
|
||||
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
|
||||
#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27)
|
||||
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25)
|
||||
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
|
||||
#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
|
||||
#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
|
||||
|
||||
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
|
||||
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
|
||||
|
||||
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
|
||||
|
||||
#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
|
||||
#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Extended Control register specific definitions.
|
||||
|
@ -78,4 +79,22 @@
|
|||
******************************************************************************/
|
||||
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
/*
|
||||
* These registers were previously wrongly named. Provide previous definitions so
|
||||
* as not to break platforms that continue using them.
|
||||
*/
|
||||
#define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1
|
||||
|
||||
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
|
||||
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
|
||||
#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
|
||||
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
|
||||
#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
|
||||
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
|
||||
#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
|
||||
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
|
||||
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
|
||||
#endif /* !ERROR_DEPRECATED */
|
||||
|
||||
#endif /* __CORTEX_A57_H__ */
|
||||
|
|
|
@ -6,49 +6,62 @@
|
|||
|
||||
#ifndef __CORTEX_A72_H__
|
||||
#define __CORTEX_A72_H__
|
||||
#include <utils_def.h>
|
||||
|
||||
/* Cortex-A72 midr for revision 0 */
|
||||
#define CORTEX_A72_MIDR 0x410FD080
|
||||
#define CORTEX_A72_MIDR 0x410FD080
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
|
||||
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
|
||||
|
||||
#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
|
||||
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
|
||||
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
|
||||
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
|
||||
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
|
||||
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
|
||||
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
|
||||
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
|
||||
#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0
|
||||
#define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0
|
||||
|
||||
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
|
||||
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
|
||||
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
|
||||
#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
|
||||
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
|
||||
|
||||
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
|
||||
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
|
||||
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
|
||||
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
|
||||
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
|
||||
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
/*
|
||||
* These registers were previously wrongly named. Provide previous definitions so
|
||||
* as not to break platforms that continue using them.
|
||||
*/
|
||||
#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR_EL1
|
||||
|
||||
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
|
||||
#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
|
||||
#endif /* !ERROR_DEPRECATED */
|
||||
|
||||
#endif /* __CORTEX_A72_H__ */
|
||||
|
|
|
@ -84,9 +84,9 @@ func a53_disable_non_temporal_hint
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A53_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A53_ACTLR_DTAH
|
||||
stcopr16 r0, r1, CORTEX_A53_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH
|
||||
stcopr16 r0, r1, CORTEX_A53_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc a53_disable_non_temporal_hint
|
||||
|
@ -118,9 +118,9 @@ func errata_a53_855873_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A53_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A53_ACTLR_ENDCCASCI
|
||||
stcopr16 r0, r1, CORTEX_A53_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI
|
||||
stcopr16 r0, r1, CORTEX_A53_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a53_855873_wa
|
||||
|
|
|
@ -67,9 +67,9 @@ func errata_a57_806969_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_806969_wa
|
||||
|
@ -111,9 +111,9 @@ func errata_a57_813420_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_DCC_AS_DCCI
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_813420_wa
|
||||
|
@ -143,9 +143,9 @@ func a57_disable_ldnp_overread
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_OVERREAD
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc a57_disable_ldnp_overread
|
||||
|
@ -172,9 +172,9 @@ func errata_a57_826974_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_826974_wa
|
||||
|
@ -201,9 +201,9 @@ func errata_a57_826977_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_826977_wa
|
||||
|
@ -230,15 +230,15 @@ func errata_a57_828024_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
/*
|
||||
* Setting the relevant bits in CORTEX_A57_ACTLR has to be done in 2
|
||||
* Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2
|
||||
* instructions here because the resulting bitmask doesn't fit in a
|
||||
* 16-bit value so it cannot be encoded in a single instruction.
|
||||
*/
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
|
||||
orr64_imm r0, r1, (CORTEX_A57_ACTLR_DIS_L1_STREAMING | CORTEX_A57_ACTLR_DIS_STREAMING)
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
|
||||
orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING)
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_828024_wa
|
||||
|
@ -265,9 +265,9 @@ func errata_a57_829520_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_829520_wa
|
||||
|
@ -294,9 +294,9 @@ func errata_a57_833471_wa
|
|||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r1, r1, CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
|
||||
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_833471_wa
|
||||
|
|
|
@ -29,9 +29,9 @@ endfunc cortex_a72_disable_l2_prefetch
|
|||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a72_disable_hw_prefetcher
|
||||
ldcopr16 r0, r1, CORTEX_A72_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
stcopr16 r0, r1, CORTEX_A72_ACTLR
|
||||
ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
|
||||
orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
stcopr16 r0, r1, CORTEX_A72_CPUACTLR
|
||||
isb
|
||||
dsb ish
|
||||
bx lr
|
||||
|
|
|
@ -93,9 +93,9 @@ func a53_disable_non_temporal_hint
|
|||
mov x17, x30
|
||||
bl check_errata_disable_non_temporal_hint
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A53_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A53_ACTLR_DTAH
|
||||
msr CORTEX_A53_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A53_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
|
||||
msr CORTEX_A53_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc a53_disable_non_temporal_hint
|
||||
|
@ -126,9 +126,9 @@ func errata_a53_855873_wa
|
|||
bl check_errata_855873
|
||||
cbz x0, 1f
|
||||
|
||||
mrs x1, CORTEX_A53_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI
|
||||
msr CORTEX_A53_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A53_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
|
||||
msr CORTEX_A53_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a53_855873_wa
|
||||
|
@ -300,7 +300,7 @@ func cortex_a53_cpu_reg_dump
|
|||
mrs x8, CORTEX_A53_ECTLR_EL1
|
||||
mrs x9, CORTEX_A53_MERRSR_EL1
|
||||
mrs x10, CORTEX_A53_L2MERRSR_EL1
|
||||
mrs x11, CORTEX_A53_ACTLR_EL1
|
||||
mrs x11, CORTEX_A53_CPUACTLR_EL1
|
||||
ret
|
||||
endfunc cortex_a53_cpu_reg_dump
|
||||
|
||||
|
|
|
@ -78,9 +78,9 @@ func errata_a57_806969_wa
|
|||
mov x17, x30
|
||||
bl check_errata_806969
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a57_806969_wa
|
||||
|
@ -120,9 +120,9 @@ func errata_a57_813420_wa
|
|||
mov x17, x30
|
||||
bl check_errata_813420
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a57_813420_wa
|
||||
|
@ -150,9 +150,9 @@ func a57_disable_ldnp_overread
|
|||
mov x17, x30
|
||||
bl check_errata_disable_ldnp_overread
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc a57_disable_ldnp_overread
|
||||
|
@ -177,9 +177,9 @@ func errata_a57_826974_wa
|
|||
mov x17, x30
|
||||
bl check_errata_826974
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a57_826974_wa
|
||||
|
@ -204,9 +204,9 @@ func errata_a57_826977_wa
|
|||
mov x17, x30
|
||||
bl check_errata_826977
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a57_826977_wa
|
||||
|
@ -231,16 +231,16 @@ func errata_a57_828024_wa
|
|||
mov x17, x30
|
||||
bl check_errata_828024
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
/*
|
||||
* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
|
||||
* instructions here because the resulting bitmask doesn't fit in a
|
||||
* 16-bit value so it cannot be encoded in a single instruction.
|
||||
*/
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
|
||||
orr x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \
|
||||
CORTEX_A57_ACTLR_DIS_STREAMING)
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
|
||||
orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
|
||||
CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING)
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a57_828024_wa
|
||||
|
@ -265,9 +265,9 @@ func errata_a57_829520_wa
|
|||
mov x17, x30
|
||||
bl check_errata_829520
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a57_829520_wa
|
||||
|
@ -292,9 +292,9 @@ func errata_a57_833471_wa
|
|||
mov x17, x30
|
||||
bl check_errata_833471
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A57_ACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
|
||||
msr CORTEX_A57_ACTLR_EL1, x1
|
||||
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a57_833471_wa
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -42,9 +42,9 @@ endfunc cortex_a72_disable_l2_prefetch
|
|||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a72_disable_hw_prefetcher
|
||||
mrs x0, CORTEX_A72_ACTLR_EL1
|
||||
orr x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
msr CORTEX_A72_ACTLR_EL1, x0
|
||||
mrs x0, CORTEX_A72_CPUACTLR_EL1
|
||||
orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
msr CORTEX_A72_CPUACTLR_EL1, x0
|
||||
isb
|
||||
dsb ish
|
||||
ret
|
||||
|
|
|
@ -19,11 +19,12 @@ func pm_asm_code _align=3
|
|||
mov x0, 0
|
||||
msr oslar_el1, x0
|
||||
|
||||
mrs x0, CORTEX_A53_ACTLR_EL1
|
||||
bic x0, x0, #(CORTEX_A53_ACTLR_RADIS | CORTEX_A53_ACTLR_L1RADIS)
|
||||
mrs x0, CORTEX_A53_CPUACTLR_EL1
|
||||
bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \
|
||||
CORTEX_A53_CPUACTLR_EL1_L1RADIS)
|
||||
orr x0, x0, #0x180000
|
||||
orr x0, x0, #0xe000
|
||||
msr CORTEX_A53_ACTLR_EL1, x0
|
||||
msr CORTEX_A53_CPUACTLR_EL1, x0
|
||||
|
||||
mrs x3, actlr_el3
|
||||
orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -316,18 +316,18 @@ func tegra_secure_entrypoint _align=6
|
|||
* entries from the branch predictor array.
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
mrs x0, CORTEX_A57_ACTLR_EL1
|
||||
mrs x0, CORTEX_A57_CPUACTLR_EL1
|
||||
orr x0, x0, #1
|
||||
msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
|
||||
dsb sy
|
||||
isb
|
||||
ic iallu /* actual invalidate */
|
||||
dsb sy
|
||||
isb
|
||||
|
||||
mrs x0, CORTEX_A57_ACTLR_EL1
|
||||
mrs x0, CORTEX_A57_CPUACTLR_EL1
|
||||
bic x0, x0, #1
|
||||
msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
|
||||
msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
|
||||
dsb sy
|
||||
isb
|
||||
|
||||
|
@ -351,7 +351,7 @@ func tegra_secure_entrypoint _align=6
|
|||
msr oslar_el1, x0 /* os lock stays 0 across warm reset */
|
||||
mov x3, #3
|
||||
movz x4, #0x8000, lsl #48
|
||||
msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */
|
||||
msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */
|
||||
isb
|
||||
msr rmr_el3, x3 /* request warm reset */
|
||||
isb
|
||||
|
|
Loading…
Reference in New Issue