Refactor fvp gic code to be a generic driver
Refactor the FVP gic code in plat/fvp/fvp_gic.c to be a generic ARM GIC driver in drivers/arm/gic/arm_gic.c. Provide the platform specific inputs in the arm_gic_setup() function so that the driver has no explicit dependency on platform code. Provide weak implementations of the platform interrupt controller API in a new file, plat/common/plat_gic.c. These simply call through to the ARM GIC driver. Move the only remaining FVP GIC function, fvp_gic_init() to plat/fvp/aarch64/fvp_common.c and remove plat/fvp/fvp_gic.c Fixes ARM-software/tf-issues#182 Change-Id: Iea82fe095fad62dd33ba9efbddd48c57717edd21
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1e8c5c4f20
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@ -29,9 +29,10 @@
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#
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#
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# TSP source files specific to FVP platform
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# TSP source files specific to FVP platform
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BL32_SOURCES += drivers/arm/gic/gic_v2.c \
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BL32_SOURCES += drivers/arm/gic/arm_gic.c \
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drivers/arm/gic/gic_v2.c \
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plat/common/aarch64/platform_mp_stack.S \
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plat/common/aarch64/platform_mp_stack.S \
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plat/common/plat_gic.c \
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plat/fvp/aarch64/fvp_common.c \
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plat/fvp/aarch64/fvp_common.c \
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plat/fvp/aarch64/fvp_helpers.S \
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plat/fvp/aarch64/fvp_helpers.S \
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plat/fvp/bl32_fvp_setup.c \
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plat/fvp/bl32_fvp_setup.c
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plat/fvp/fvp_gic.c
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@ -158,9 +158,9 @@ performed.
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* `V`: Verbose build. If assigned anything other than 0, the build commands
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* `V`: Verbose build. If assigned anything other than 0, the build commands
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are printed. Default is 0
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are printed. Default is 0
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* `FVP_GIC_ARCH`: Choice of ARM GIC architecture version used by the FVP port
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* `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM GIC
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for implementing the platform GIC API. This API is used by the interrupt
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driver for implementing the platform GIC API. This API is used
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management framework. Default is 2 i.e. version 2.0
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by the interrupt management framework. Default is 2 i.e. version 2.0.
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* `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management
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* `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management
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framework to enable passing of the interrupt id to its handler. The id is
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framework to enable passing of the interrupt id to its handler. The id is
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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@ -28,7 +28,9 @@
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <debug.h>
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@ -36,10 +38,15 @@
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#include <gic_v3.h>
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#include <gic_v3.h>
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#include <interrupt_mgmt.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <platform.h>
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#include <plat_config.h>
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#include <stdint.h>
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#include <stdint.h>
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#include "fvp_def.h"
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#include "fvp_private.h"
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static unsigned int g_gicc_base;
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static unsigned int g_gicd_base;
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static unsigned long g_gicr_base;
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static const unsigned int *g_irq_sec_ptr;
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static unsigned int g_num_irqs;
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/*******************************************************************************
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/*******************************************************************************
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* This function does some minimal GICv3 configuration. The Firmware itself does
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* This function does some minimal GICv3 configuration. The Firmware itself does
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@ -47,7 +54,7 @@
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* provided by GICv3. This function allows software (like Linux) in later stages
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* provided by GICv3. This function allows software (like Linux) in later stages
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* to use full GICv3 features.
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* to use full GICv3 features.
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******************************************************************************/
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******************************************************************************/
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void gicv3_cpuif_setup(void)
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static void gicv3_cpuif_setup(void)
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{
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{
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unsigned int scr_val, val;
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unsigned int scr_val, val;
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uintptr_t base;
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uintptr_t base;
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@ -60,7 +67,8 @@ void gicv3_cpuif_setup(void)
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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* per CPU.
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*/
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*/
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base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
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assert(g_gicr_base);
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base = gicv3_get_rdist(g_gicr_base, read_mpidr());
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if (base == (uintptr_t)NULL) {
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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/* No re-distributor base address. This interface cannot be
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* configured.
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* configured.
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@ -76,9 +84,8 @@ void gicv3_cpuif_setup(void)
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/* We need to wait for ChildrenAsleep to clear. */
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/* We need to wait for ChildrenAsleep to clear. */
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val = gicr_read_waker(base);
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val = gicr_read_waker(base);
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while (val & WAKER_CA) {
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while (val & WAKER_CA)
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val = gicr_read_waker(base);
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val = gicr_read_waker(base);
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}
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/*
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/*
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* We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
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* We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
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@ -104,7 +111,7 @@ void gicv3_cpuif_setup(void)
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write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
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write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
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write_icc_pmr_el1(GIC_PRI_MASK);
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write_icc_pmr_el1(GIC_PRI_MASK);
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isb(); /* commite ICC_* changes before setting NS=0 */
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isb(); /* commit ICC_* changes before setting NS=0 */
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/* Restore SCR_EL3 */
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/* Restore SCR_EL3 */
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write_scr(scr_val);
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write_scr(scr_val);
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@ -115,7 +122,7 @@ void gicv3_cpuif_setup(void)
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* This function does some minimal GICv3 configuration when cores go
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* This function does some minimal GICv3 configuration when cores go
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* down.
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* down.
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******************************************************************************/
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******************************************************************************/
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void gicv3_cpuif_deactivate(void)
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static void gicv3_cpuif_deactivate(void)
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{
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{
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unsigned int val;
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unsigned int val;
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uintptr_t base;
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uintptr_t base;
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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* per CPU.
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*/
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*/
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base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
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assert(g_gicr_base);
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base = gicv3_get_rdist(g_gicr_base, read_mpidr());
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if (base == (uintptr_t)NULL) {
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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/* No re-distributor base address. This interface cannot be
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* configured.
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* configured.
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/* We need to wait for ChildrenAsleep to set. */
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/* We need to wait for ChildrenAsleep to set. */
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val = gicr_read_waker(base);
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val = gicr_read_waker(base);
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while ((val & WAKER_CA) == 0) {
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while ((val & WAKER_CA) == 0)
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val = gicr_read_waker(base);
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val = gicr_read_waker(base);
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}
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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* Enable secure interrupts and use FIQs to route them. Disable legacy bypass
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* Enable secure interrupts and use FIQs to route them. Disable legacy bypass
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* and set the priority mask register to allow all interrupts to trickle in.
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* and set the priority mask register to allow all interrupts to trickle in.
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******************************************************************************/
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******************************************************************************/
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void gic_cpuif_setup(unsigned int gicc_base)
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void arm_gic_cpuif_setup(void)
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{
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{
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unsigned int val;
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unsigned int val;
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val = gicc_read_iidr(gicc_base);
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assert(g_gicc_base);
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val = gicc_read_iidr(g_gicc_base);
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/*
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/*
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* If GICv3 we need to do a bit of additional setup. We want to
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* If GICv3 we need to do a bit of additional setup. We want to
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* allow default GICv2 behaviour but allow the next stage to
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* allow default GICv2 behaviour but allow the next stage to
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* enable full gicv3 features.
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* enable full gicv3 features.
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*/
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
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gicv3_cpuif_setup();
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gicv3_cpuif_setup();
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}
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val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_pmr(gicc_base, GIC_PRI_MASK);
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gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
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gicc_write_ctlr(gicc_base, val);
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gicc_write_ctlr(g_gicc_base, val);
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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******************************************************************************/
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void gic_cpuif_deactivate(unsigned int gicc_base)
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void arm_gic_cpuif_deactivate(void)
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{
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{
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unsigned int val;
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unsigned int val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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/* Disable secure, non-secure interrupts and disable their bypass */
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val = gicc_read_ctlr(gicc_base);
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assert(g_gicc_base);
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val = gicc_read_ctlr(g_gicc_base);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(gicc_base, val);
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gicc_write_ctlr(g_gicc_base, val);
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val = gicc_read_iidr(gicc_base);
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val = gicc_read_iidr(g_gicc_base);
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/*
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/*
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* If GICv3 we need to do a bit of additional setup. Make sure the
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* If GICv3 we need to do a bit of additional setup. Make sure the
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* RDIST is put to sleep.
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* RDIST is put to sleep.
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*/
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
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gicv3_cpuif_deactivate();
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gicv3_cpuif_deactivate();
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}
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure interrupts & enables them.
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* boot/hotplug. This marks out the secure interrupts & enables them.
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******************************************************************************/
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******************************************************************************/
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void gic_pcpu_distif_setup(unsigned int gicd_base)
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void arm_gic_pcpu_distif_setup(void)
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{
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{
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gicd_write_igroupr(gicd_base, 0, ~0);
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unsigned int index, irq_num;
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gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER);
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assert(g_gicd_base);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0);
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gicd_write_igroupr(g_gicd_base, 0, ~0);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY);
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assert(g_irq_sec_ptr);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY);
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for (index = 0; index < g_num_irqs; index++) {
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY);
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irq_num = g_irq_sec_ptr[index];
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY);
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if (irq_num < MIN_SPI_ID) {
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY);
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/* We have an SGI or a PPI */
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY);
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gicd_clr_igroupr(g_gicd_base, irq_num);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(g_gicd_base, irq_num,
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY);
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GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_isenabler(g_gicd_base, irq_num);
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}
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gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER);
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}
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7);
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* then enables the secure GIC distributor interface.
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* then enables the secure GIC distributor interface.
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******************************************************************************/
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******************************************************************************/
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void gic_distif_setup(unsigned int gicd_base)
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static void arm_gic_distif_setup(void)
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{
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{
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unsigned int ctr, num_ints, ctlr;
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unsigned int num_ints, ctlr, index, irq_num;
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/* Disable the distributor before going further */
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/* Disable the distributor before going further */
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ctlr = gicd_read_ctlr(gicd_base);
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assert(g_gicd_base);
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ctlr = gicd_read_ctlr(g_gicd_base);
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ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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gicd_write_ctlr(gicd_base, ctlr);
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gicd_write_ctlr(g_gicd_base, ctlr);
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/*
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/*
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* Mark out non-secure interrupts. Calculate number of
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* Mark out non-secure interrupts. Calculate number of
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* IGROUPR registers to consider. Will be equal to the
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* IGROUPR registers to consider. Will be equal to the
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* number of IT_LINES
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* number of IT_LINES
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*/
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*/
|
||||||
num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
|
num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
|
||||||
num_ints++;
|
num_ints++;
|
||||||
for (ctr = 0; ctr < num_ints; ctr++)
|
for (index = 0; index < num_ints; index++)
|
||||||
gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0);
|
gicd_write_igroupr(g_gicd_base, index << IGROUPR_SHIFT, ~0);
|
||||||
|
|
||||||
/* Configure secure interrupts now */
|
/* Configure secure interrupts now */
|
||||||
gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG);
|
assert(g_irq_sec_ptr);
|
||||||
gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY);
|
for (index = 0; index < g_num_irqs; index++) {
|
||||||
gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
|
irq_num = g_irq_sec_ptr[index];
|
||||||
|
if (irq_num >= MIN_SPI_ID) {
|
||||||
|
/* We have an SPI */
|
||||||
|
gicd_clr_igroupr(g_gicd_base, irq_num);
|
||||||
|
gicd_set_ipriorityr(g_gicd_base, irq_num,
|
||||||
|
GIC_HIGHEST_SEC_PRIORITY);
|
||||||
|
gicd_set_itargetsr(g_gicd_base, irq_num,
|
||||||
platform_get_core_pos(read_mpidr()));
|
platform_get_core_pos(read_mpidr()));
|
||||||
gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
|
gicd_set_isenabler(g_gicd_base, irq_num);
|
||||||
gic_pcpu_distif_setup(gicd_base);
|
}
|
||||||
|
}
|
||||||
|
arm_gic_pcpu_distif_setup();
|
||||||
|
|
||||||
gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
|
gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void gic_setup(void)
|
/*******************************************************************************
|
||||||
|
* Initialize the ARM GIC driver with the provided platform inputs
|
||||||
|
******************************************************************************/
|
||||||
|
void arm_gic_init(unsigned int gicc_base,
|
||||||
|
unsigned int gicd_base,
|
||||||
|
unsigned long gicr_base,
|
||||||
|
const unsigned int *irq_sec_ptr,
|
||||||
|
unsigned int num_irqs
|
||||||
|
)
|
||||||
{
|
{
|
||||||
gic_cpuif_setup(get_plat_config()->gicc_base);
|
assert(gicc_base);
|
||||||
gic_distif_setup(get_plat_config()->gicd_base);
|
assert(gicd_base);
|
||||||
|
assert(gicr_base);
|
||||||
|
assert(irq_sec_ptr);
|
||||||
|
g_gicc_base = gicc_base;
|
||||||
|
g_gicd_base = gicd_base;
|
||||||
|
g_gicr_base = gicr_base;
|
||||||
|
g_irq_sec_ptr = irq_sec_ptr;
|
||||||
|
g_num_irqs = num_irqs;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Setup the ARM GIC CPU and distributor interfaces.
|
||||||
|
******************************************************************************/
|
||||||
|
void arm_gic_setup(void)
|
||||||
|
{
|
||||||
|
arm_gic_cpuif_setup();
|
||||||
|
arm_gic_distif_setup();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
|
* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
|
||||||
* The interrupt controller knows which pin/line it uses to signal a type of
|
* The interrupt controller knows which pin/line it uses to signal a type of
|
||||||
* interrupt. The platform knows which interrupt controller type is being used
|
* interrupt. This function provides a common implementation of
|
||||||
* in a particular security state e.g. with an ARM GIC, normal world could use
|
* plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
|
||||||
* the GICv2 features while the secure world could use GICv3 features and vice
|
* across platforms. It lets the interrupt management framework determine
|
||||||
* versa.
|
* for a type of interrupt and security state, which line should be used in the
|
||||||
* This function is exported by the platform to let the interrupt management
|
* SCR_EL3 to control its routing to EL3. The interrupt line is represented as
|
||||||
* framework determine for a type of interrupt and security state, which line
|
* the bit position of the IRQ or FIQ bit in the SCR_EL3.
|
||||||
* should be used in the SCR_EL3 to control its routing to EL3. The interrupt
|
|
||||||
* line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3.
|
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
|
uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
|
||||||
|
uint32_t security_state)
|
||||||
{
|
{
|
||||||
uint32_t gicc_base = get_plat_config()->gicc_base;
|
|
||||||
|
|
||||||
assert(type == INTR_TYPE_S_EL1 ||
|
assert(type == INTR_TYPE_S_EL1 ||
|
||||||
type == INTR_TYPE_EL3 ||
|
type == INTR_TYPE_EL3 ||
|
||||||
type == INTR_TYPE_NS);
|
type == INTR_TYPE_NS);
|
||||||
|
@ -307,24 +329,25 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
|
||||||
* both normal and secure worlds are using ARM GICv2. This parameter
|
* both normal and secure worlds are using ARM GICv2. This parameter
|
||||||
* will be used when the secure world starts using GICv3.
|
* will be used when the secure world starts using GICv3.
|
||||||
*/
|
*/
|
||||||
#if FVP_GIC_ARCH == 2
|
#if ARM_GIC_ARCH == 2
|
||||||
return gicv2_interrupt_type_to_line(gicc_base, type);
|
return gicv2_interrupt_type_to_line(g_gicc_base, type);
|
||||||
#else
|
#else
|
||||||
#error "Invalid GIC architecture version specified for FVP port"
|
#error "Invalid ARM GIC architecture version specified for platform port"
|
||||||
#endif
|
#endif /* ARM_GIC_ARCH */
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FVP_GIC_ARCH == 2
|
#if ARM_GIC_ARCH == 2
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* This function returns the type of the highest priority pending interrupt at
|
* This function returns the type of the highest priority pending interrupt at
|
||||||
* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
|
* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
|
||||||
* interrupt pending.
|
* interrupt pending.
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
uint32_t plat_ic_get_pending_interrupt_type(void)
|
uint32_t arm_gic_get_pending_interrupt_type(void)
|
||||||
{
|
{
|
||||||
uint32_t id;
|
uint32_t id;
|
||||||
|
|
||||||
id = gicc_read_hppir(get_plat_config()->gicc_base);
|
assert(g_gicc_base);
|
||||||
|
id = gicc_read_hppir(g_gicc_base);
|
||||||
|
|
||||||
/* Assume that all secure interrupts are S-EL1 interrupts */
|
/* Assume that all secure interrupts are S-EL1 interrupts */
|
||||||
if (id < 1022)
|
if (id < 1022)
|
||||||
|
@ -341,12 +364,12 @@ uint32_t plat_ic_get_pending_interrupt_type(void)
|
||||||
* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
|
* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
|
||||||
* interrupt pending.
|
* interrupt pending.
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
uint32_t plat_ic_get_pending_interrupt_id(void)
|
uint32_t arm_gic_get_pending_interrupt_id(void)
|
||||||
{
|
{
|
||||||
uint32_t id, gicc_base;
|
uint32_t id;
|
||||||
|
|
||||||
gicc_base = get_plat_config()->gicc_base;
|
assert(g_gicc_base);
|
||||||
id = gicc_read_hppir(gicc_base);
|
id = gicc_read_hppir(g_gicc_base);
|
||||||
|
|
||||||
if (id < 1022)
|
if (id < 1022)
|
||||||
return id;
|
return id;
|
||||||
|
@ -358,26 +381,27 @@ uint32_t plat_ic_get_pending_interrupt_id(void)
|
||||||
* Find out which non-secure interrupt it is under the assumption that
|
* Find out which non-secure interrupt it is under the assumption that
|
||||||
* the GICC_CTLR.AckCtl bit is 0.
|
* the GICC_CTLR.AckCtl bit is 0.
|
||||||
*/
|
*/
|
||||||
return gicc_read_ahppir(gicc_base);
|
return gicc_read_ahppir(g_gicc_base);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* This functions reads the GIC cpu interface Interrupt Acknowledge register
|
* This functions reads the GIC cpu interface Interrupt Acknowledge register
|
||||||
* to start handling the pending interrupt. It returns the contents of the IAR.
|
* to start handling the pending interrupt. It returns the contents of the IAR.
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
uint32_t plat_ic_acknowledge_interrupt(void)
|
uint32_t arm_gic_acknowledge_interrupt(void)
|
||||||
{
|
{
|
||||||
return gicc_read_IAR(get_plat_config()->gicc_base);
|
assert(g_gicc_base);
|
||||||
|
return gicc_read_IAR(g_gicc_base);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* This functions writes the GIC cpu interface End Of Interrupt register with
|
* This functions writes the GIC cpu interface End Of Interrupt register with
|
||||||
* the passed value to finish handling the active interrupt
|
* the passed value to finish handling the active interrupt
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
void plat_ic_end_of_interrupt(uint32_t id)
|
void arm_gic_end_of_interrupt(uint32_t id)
|
||||||
{
|
{
|
||||||
gicc_write_EOIR(get_plat_config()->gicc_base, id);
|
assert(g_gicc_base);
|
||||||
return;
|
gicc_write_EOIR(g_gicc_base, id);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
|
@ -385,11 +409,12 @@ void plat_ic_end_of_interrupt(uint32_t id)
|
||||||
* this interrupt has been configured under by the interrupt controller i.e.
|
* this interrupt has been configured under by the interrupt controller i.e.
|
||||||
* group0 or group1.
|
* group0 or group1.
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
uint32_t plat_ic_get_interrupt_type(uint32_t id)
|
uint32_t arm_gic_get_interrupt_type(uint32_t id)
|
||||||
{
|
{
|
||||||
uint32_t group;
|
uint32_t group;
|
||||||
|
|
||||||
group = gicd_get_igroupr(get_plat_config()->gicd_base, id);
|
assert(g_gicd_base);
|
||||||
|
group = gicd_get_igroupr(g_gicd_base, id);
|
||||||
|
|
||||||
/* Assume that all secure interrupts are S-EL1 interrupts */
|
/* Assume that all secure interrupts are S-EL1 interrupts */
|
||||||
if (group == GRP0)
|
if (group == GRP0)
|
||||||
|
@ -399,5 +424,5 @@ uint32_t plat_ic_get_interrupt_type(uint32_t id)
|
||||||
}
|
}
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#error "Invalid GIC architecture version specified for FVP port"
|
#error "Invalid ARM GIC architecture version specified for platform port"
|
||||||
#endif
|
#endif /* ARM_GIC_ARCH */
|
|
@ -0,0 +1,57 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
* to endorse or promote products derived from this software without specific
|
||||||
|
* prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ARM_GIC_H__
|
||||||
|
#define __ARM_GIC_H__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Function declarations
|
||||||
|
******************************************************************************/
|
||||||
|
void arm_gic_init(unsigned int gicc_base,
|
||||||
|
unsigned int gicd_base,
|
||||||
|
unsigned long gicr_base,
|
||||||
|
const unsigned int *irq_sec_ptr,
|
||||||
|
unsigned int num_irqs);
|
||||||
|
void arm_gic_setup(void);
|
||||||
|
void arm_gic_cpuif_deactivate(void);
|
||||||
|
void arm_gic_cpuif_setup(void);
|
||||||
|
void arm_gic_pcpu_distif_setup(void);
|
||||||
|
|
||||||
|
uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
|
||||||
|
uint32_t security_state);
|
||||||
|
uint32_t arm_gic_get_pending_interrupt_type(void);
|
||||||
|
uint32_t arm_gic_get_pending_interrupt_id(void);
|
||||||
|
uint32_t arm_gic_acknowledge_interrupt(void);
|
||||||
|
void arm_gic_end_of_interrupt(uint32_t id);
|
||||||
|
uint32_t arm_gic_get_interrupt_type(uint32_t id);
|
||||||
|
|
||||||
|
#endif /* __GIC_H__ */
|
|
@ -36,6 +36,10 @@
|
||||||
#define MAX_PPIS 14
|
#define MAX_PPIS 14
|
||||||
#define MAX_SGIS 16
|
#define MAX_SGIS 16
|
||||||
|
|
||||||
|
#define MIN_SGI_ID 0
|
||||||
|
#define MIN_PPI_ID 16
|
||||||
|
#define MIN_SPI_ID 32
|
||||||
|
|
||||||
#define GRP0 0
|
#define GRP0 0
|
||||||
#define GRP1 1
|
#define GRP1 1
|
||||||
#define GIC_PRI_MASK 0xff
|
#define GIC_PRI_MASK 0xff
|
||||||
|
|
|
@ -0,0 +1,73 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
* to endorse or promote products derived from this software without specific
|
||||||
|
* prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
#include <arm_gic.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The following platform GIC functions are weakly defined. They
|
||||||
|
* provide typical implementations that may be re-used by multiple
|
||||||
|
* platforms but may also be overridden by a platform if required.
|
||||||
|
*/
|
||||||
|
#pragma weak plat_ic_get_pending_interrupt_id
|
||||||
|
#pragma weak plat_ic_get_pending_interrupt_type
|
||||||
|
#pragma weak plat_ic_acknowledge_interrupt
|
||||||
|
#pragma weak plat_ic_get_interrupt_type
|
||||||
|
#pragma weak plat_ic_end_of_interrupt
|
||||||
|
#pragma weak plat_interrupt_type_to_line
|
||||||
|
|
||||||
|
uint32_t plat_ic_get_pending_interrupt_id(void)
|
||||||
|
{
|
||||||
|
return arm_gic_get_pending_interrupt_id();
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t plat_ic_get_pending_interrupt_type(void)
|
||||||
|
{
|
||||||
|
return arm_gic_get_pending_interrupt_type();
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t plat_ic_acknowledge_interrupt(void)
|
||||||
|
{
|
||||||
|
return arm_gic_acknowledge_interrupt();
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t plat_ic_get_interrupt_type(uint32_t id)
|
||||||
|
{
|
||||||
|
return arm_gic_get_interrupt_type(id);
|
||||||
|
}
|
||||||
|
|
||||||
|
void plat_ic_end_of_interrupt(uint32_t id)
|
||||||
|
{
|
||||||
|
arm_gic_end_of_interrupt(id);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t plat_interrupt_type_to_line(uint32_t type,
|
||||||
|
uint32_t security_state)
|
||||||
|
{
|
||||||
|
return arm_gic_interrupt_type_to_line(type, security_state);
|
||||||
|
}
|
|
@ -30,6 +30,7 @@
|
||||||
|
|
||||||
#include <arch.h>
|
#include <arch.h>
|
||||||
#include <arch_helpers.h>
|
#include <arch_helpers.h>
|
||||||
|
#include <arm_gic.h>
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
#include <bl_common.h>
|
#include <bl_common.h>
|
||||||
#include <cci400.h>
|
#include <cci400.h>
|
||||||
|
@ -77,6 +78,23 @@ const mmap_region_t fvp_mmap[] = {
|
||||||
{0}
|
{0}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* Array of secure interrupts to be configured by the gic driver */
|
||||||
|
const unsigned int irq_sec_array[] = {
|
||||||
|
IRQ_TZ_WDOG,
|
||||||
|
IRQ_SEC_PHY_TIMER,
|
||||||
|
IRQ_SEC_SGI_0,
|
||||||
|
IRQ_SEC_SGI_1,
|
||||||
|
IRQ_SEC_SGI_2,
|
||||||
|
IRQ_SEC_SGI_3,
|
||||||
|
IRQ_SEC_SGI_4,
|
||||||
|
IRQ_SEC_SGI_5,
|
||||||
|
IRQ_SEC_SGI_6,
|
||||||
|
IRQ_SEC_SGI_7
|
||||||
|
};
|
||||||
|
|
||||||
|
const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
|
||||||
|
sizeof(irq_sec_array[0]);
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Macro generating the code for the function setting up the pagetables as per
|
* Macro generating the code for the function setting up the pagetables as per
|
||||||
* the platform memory map & initialize the mmu, for the given exception level
|
* the platform memory map & initialize the mmu, for the given exception level
|
||||||
|
@ -235,6 +253,15 @@ void fvp_cci_setup(void)
|
||||||
cci_enable_coherency(read_mpidr());
|
cci_enable_coherency(read_mpidr());
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void fvp_gic_init(void)
|
||||||
|
{
|
||||||
|
arm_gic_init(plat_config.gicc_base,
|
||||||
|
plat_config.gicd_base,
|
||||||
|
BASE_GICR_BASE,
|
||||||
|
irq_sec_array,
|
||||||
|
num_sec_irqs);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Gets SPSR for BL32 entry
|
* Gets SPSR for BL32 entry
|
||||||
|
|
|
@ -30,6 +30,7 @@
|
||||||
|
|
||||||
#include <arch.h>
|
#include <arch.h>
|
||||||
#include <arch_helpers.h>
|
#include <arch_helpers.h>
|
||||||
|
#include <arm_gic.h>
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
#include <bl_common.h>
|
#include <bl_common.h>
|
||||||
#include <bl31.h>
|
#include <bl31.h>
|
||||||
|
@ -183,7 +184,8 @@ void bl31_platform_setup(void)
|
||||||
unsigned int reg_val;
|
unsigned int reg_val;
|
||||||
|
|
||||||
/* Initialize the gic cpu and distributor interfaces */
|
/* Initialize the gic cpu and distributor interfaces */
|
||||||
gic_setup();
|
fvp_gic_init();
|
||||||
|
arm_gic_setup();
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TODO: Configure the CLCD before handing control to
|
* TODO: Configure the CLCD before handing control to
|
||||||
|
|
|
@ -83,7 +83,7 @@ void bl32_early_platform_setup(void)
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
void bl32_platform_setup(void)
|
void bl32_platform_setup(void)
|
||||||
{
|
{
|
||||||
|
fvp_gic_init();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
|
|
|
@ -29,6 +29,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <arch_helpers.h>
|
#include <arch_helpers.h>
|
||||||
|
#include <arm_gic.h>
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
#include <bakery_lock.h>
|
#include <bakery_lock.h>
|
||||||
#include <cci400.h>
|
#include <cci400.h>
|
||||||
|
@ -130,7 +131,7 @@ int fvp_affinst_off(unsigned long mpidr,
|
||||||
unsigned int state)
|
unsigned int state)
|
||||||
{
|
{
|
||||||
int rc = PSCI_E_SUCCESS;
|
int rc = PSCI_E_SUCCESS;
|
||||||
unsigned int gicc_base, ectlr;
|
unsigned int ectlr;
|
||||||
|
|
||||||
switch (afflvl) {
|
switch (afflvl) {
|
||||||
case MPIDR_AFFLVL1:
|
case MPIDR_AFFLVL1:
|
||||||
|
@ -168,8 +169,7 @@ int fvp_affinst_off(unsigned long mpidr,
|
||||||
* Prevent interrupts from spuriously waking up
|
* Prevent interrupts from spuriously waking up
|
||||||
* this cpu
|
* this cpu
|
||||||
*/
|
*/
|
||||||
gicc_base = get_plat_config()->gicc_base;
|
arm_gic_cpuif_deactivate();
|
||||||
gic_cpuif_deactivate(gicc_base);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Program the power controller to power this
|
* Program the power controller to power this
|
||||||
|
@ -205,7 +205,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
|
||||||
unsigned int state)
|
unsigned int state)
|
||||||
{
|
{
|
||||||
int rc = PSCI_E_SUCCESS;
|
int rc = PSCI_E_SUCCESS;
|
||||||
unsigned int gicc_base, ectlr;
|
unsigned int ectlr;
|
||||||
unsigned long linear_id;
|
unsigned long linear_id;
|
||||||
mailbox_t *fvp_mboxes;
|
mailbox_t *fvp_mboxes;
|
||||||
|
|
||||||
|
@ -251,8 +251,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
|
||||||
* Prevent interrupts from spuriously waking up
|
* Prevent interrupts from spuriously waking up
|
||||||
* this cpu
|
* this cpu
|
||||||
*/
|
*/
|
||||||
gicc_base = get_plat_config()->gicc_base;
|
arm_gic_cpuif_deactivate();
|
||||||
gic_cpuif_deactivate(gicc_base);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Program the power controller to power this
|
* Program the power controller to power this
|
||||||
|
@ -284,7 +283,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
|
||||||
int rc = PSCI_E_SUCCESS;
|
int rc = PSCI_E_SUCCESS;
|
||||||
unsigned long linear_id;
|
unsigned long linear_id;
|
||||||
mailbox_t *fvp_mboxes;
|
mailbox_t *fvp_mboxes;
|
||||||
unsigned int gicd_base, gicc_base, ectlr;
|
unsigned int ectlr;
|
||||||
|
|
||||||
switch (afflvl) {
|
switch (afflvl) {
|
||||||
|
|
||||||
|
@ -339,12 +338,10 @@ int fvp_affinst_on_finish(unsigned long mpidr,
|
||||||
sizeof(unsigned long));
|
sizeof(unsigned long));
|
||||||
|
|
||||||
/* Enable the gic cpu interface */
|
/* Enable the gic cpu interface */
|
||||||
gicc_base = get_plat_config()->gicc_base;
|
arm_gic_cpuif_setup();
|
||||||
gic_cpuif_setup(gicc_base);
|
|
||||||
|
|
||||||
/* TODO: This setup is needed only after a cold boot */
|
/* TODO: This setup is needed only after a cold boot */
|
||||||
gicd_base = get_plat_config()->gicd_base;
|
arm_gic_pcpu_distif_setup();
|
||||||
gic_pcpu_distif_setup(gicd_base);
|
|
||||||
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
|
|
@ -79,11 +79,7 @@ int fvp_config_setup(void);
|
||||||
|
|
||||||
void fvp_cci_setup(void);
|
void fvp_cci_setup(void);
|
||||||
|
|
||||||
/* Declarations for fvp_gic.c */
|
void fvp_gic_init(void);
|
||||||
void gic_cpuif_deactivate(unsigned int);
|
|
||||||
void gic_cpuif_setup(unsigned int);
|
|
||||||
void gic_pcpu_distif_setup(unsigned int);
|
|
||||||
void gic_setup(void);
|
|
||||||
|
|
||||||
/* Declarations for fvp_topology.c */
|
/* Declarations for fvp_topology.c */
|
||||||
int fvp_setup_topology(void);
|
int fvp_setup_topology(void);
|
||||||
|
|
|
@ -69,12 +69,13 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \
|
||||||
plat/fvp/aarch64/fvp_common.c
|
plat/fvp/aarch64/fvp_common.c
|
||||||
|
|
||||||
BL31_SOURCES += drivers/arm/cci400/cci400.c \
|
BL31_SOURCES += drivers/arm/cci400/cci400.c \
|
||||||
|
drivers/arm/gic/arm_gic.c \
|
||||||
drivers/arm/gic/gic_v2.c \
|
drivers/arm/gic/gic_v2.c \
|
||||||
drivers/arm/gic/gic_v3.c \
|
drivers/arm/gic/gic_v3.c \
|
||||||
drivers/arm/tzc400/tzc400.c \
|
drivers/arm/tzc400/tzc400.c \
|
||||||
|
plat/common/plat_gic.c \
|
||||||
plat/common/aarch64/platform_mp_stack.S \
|
plat/common/aarch64/platform_mp_stack.S \
|
||||||
plat/fvp/bl31_fvp_setup.c \
|
plat/fvp/bl31_fvp_setup.c \
|
||||||
plat/fvp/fvp_gic.c \
|
|
||||||
plat/fvp/fvp_pm.c \
|
plat/fvp/fvp_pm.c \
|
||||||
plat/fvp/fvp_security.c \
|
plat/fvp/fvp_security.c \
|
||||||
plat/fvp/fvp_topology.c \
|
plat/fvp/fvp_topology.c \
|
||||||
|
@ -82,7 +83,7 @@ BL31_SOURCES += drivers/arm/cci400/cci400.c \
|
||||||
plat/fvp/aarch64/fvp_common.c \
|
plat/fvp/aarch64/fvp_common.c \
|
||||||
plat/fvp/drivers/pwrc/fvp_pwrc.c
|
plat/fvp/drivers/pwrc/fvp_pwrc.c
|
||||||
|
|
||||||
# Flag used by the FVP port to determine the version of ARM GIC architecture
|
# Flag used by the platform port to determine the version of ARM GIC
|
||||||
# to use for interrupt management in EL3.
|
# architecture to use for interrupt management in EL3.
|
||||||
FVP_GIC_ARCH := 2
|
ARM_GIC_ARCH := 2
|
||||||
$(eval $(call add_define,FVP_GIC_ARCH))
|
$(eval $(call add_define,ARM_GIC_ARCH))
|
||||||
|
|
Loading…
Reference in New Issue