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feat(st-uart): manage oversampling by 8 

UART oversampling by 8 allows higher baud rates for UART. This is
required when (UART freq / baudrate) <= 16. In this case the OVER8 bit
needs to be enabled in CR1 register. And the BRR register management is
different:
USARTDIV = (2 * UART freq / baudrate) (with div round nearest)
BRR[15:4] = USARTDIV[15:4]
BRR[3] = 0
BRR[2:0] = USARTDIV[3:0] >> 1

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia3fbeeb73a36a4dc485c7ba428c531e65b6f6c09
This commit is contained in:
Yann Gautier 2022-02-28 18:28:06 +01:00 committed by Yann Gautier
parent af7775ab53
commit 1f60d1bd33
1 changed files with 15 additions and 0 deletions
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15
drivers/st/uart/aarch32/stm32_console.S
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@ -70,6 +70,21 @@ func console_stm32_core_init
lsr r3, r2, #1
add r3, r1, r3
udiv r3, r3, r2
cmp r3, #16
bhi 2f
/* Oversampling 8 */
/* Divisor = (2 * Uart clock + (baudrate / 2)) / baudrate */
lsr r3, r2, #1
add r3, r3, r1, lsl #1
udiv r3, r3, r2
and r1, r3, #USART_BRR_DIV_FRACTION
lsr r1, r1, #1
bic r3, r3, #USART_BRR_DIV_FRACTION
orr r3, r3, r1
ldr r1, [r0, #USART_CR1]
orr r1, r1, #USART_CR1_OVER8
str r1, [r0, #USART_CR1]
2:
str r3, [r0, #USART_BRR]
/* Enable UART */
ldr r3, [r0, #USART_CR1]