Merge "Provide a hint to power controller for DSU cluster power down" into integration
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commit
1f915222ae
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@ -701,4 +701,14 @@
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#define AMEVTYPER1E p15, 0, c13, c15, 6
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#define AMEVTYPER1F p15, 0, c13, c15, 7
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/*******************************************************************************
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* Definitions for DynamicIQ Shared Unit registers
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******************************************************************************/
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#define CLUSTERPWRDN p15, 0, c15, c3, 6
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/* CLUSTERPWRDN register definitions */
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#define DSU_CLUSTER_PWR_OFF 0
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#define DSU_CLUSTER_PWR_ON 1
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#define DSU_CLUSTER_PWR_MASK U(1)
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#endif /* ARCH_H */
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@ -336,6 +336,11 @@ DEFINE_DCOP_PARAM_FUNC(cvac, DCCIMVAC)
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DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
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#endif
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/*
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* DynamIQ Shared Unit power management
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*/
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DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN)
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/* Previously defined accessor functions with incomplete register names */
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#define dsb() dsbsy()
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#define dmb() dmbsy()
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@ -947,4 +947,14 @@
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#define RGSR_EL1 S3_0_C1_C0_5
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#define GCR_EL1 S3_0_C1_C0_6
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/*******************************************************************************
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* Definitions for DynamicIQ Shared Unit registers
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******************************************************************************/
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#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
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/* CLUSTERPWRDN_EL1 register definitions */
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#define DSU_CLUSTER_PWR_OFF 0
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#define DSU_CLUSTER_PWR_ON 1
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#define DSU_CLUSTER_PWR_MASK U(1)
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#endif /* ARCH_H */
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@ -520,6 +520,9 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
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/* DynamIQ Shared Unit power management */
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DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
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#define IS_IN_EL(x) \
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(GET_EL(read_CurrentEl()) == MODE_EL##x)
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@ -582,4 +585,7 @@ static inline uint64_t el_implemented(unsigned int el)
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#define read_cpacr() read_cpacr_el1()
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#define write_cpacr(_v) write_cpacr_el1(_v)
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#define read_clusterpwrdn() read_clusterpwrdn_el1()
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#define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
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#endif /* ARCH_HELPERS_H */
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@ -64,6 +64,25 @@ static void fvp_cluster_pwrdwn_common(void)
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/* Disable coherency if this cluster is to be turned off */
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fvp_interconnect_disable();
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#if HW_ASSISTED_COHERENCY
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uint32_t reg;
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/*
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* If we have determined this core to be the last man standing and we
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* intend to power down the cluster proactively, we provide a hint to
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* the power controller that cluster power is not required when all
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* cores are powered down.
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* Note that this is only an advisory to power controller and is supported
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* by SoCs with DynamIQ Shared Units only.
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*/
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reg = read_clusterpwrdn();
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/* Clear and set bit 0 : Cluster power not required */
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reg &= ~DSU_CLUSTER_PWR_MASK;
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reg |= DSU_CLUSTER_PWR_OFF;
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write_clusterpwrdn(reg);
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#endif
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/* Program the power controller to turn the cluster off */
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fvp_pwrc_write_pcoffr(mpidr);
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}
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@ -124,8 +124,28 @@ static void css_power_down_common(const psci_power_state_t *target_state)
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plat_arm_gic_cpuif_disable();
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/* Cluster is to be turned off, so disable coherency */
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if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
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if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
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plat_arm_interconnect_exit_coherency();
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#if HW_ASSISTED_COHERENCY
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uint32_t reg;
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/*
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* If we have determined this core to be the last man standing and we
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* intend to power down the cluster proactively, we provide a hint to
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* the power controller that cluster power is not required when all
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* cores are powered down.
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* Note that this is only an advisory to power controller and is supported
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* by SoCs with DynamIQ Shared Units only.
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*/
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reg = read_clusterpwrdn();
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/* Clear and set bit 0 : Cluster power not required */
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reg &= ~DSU_CLUSTER_PWR_MASK;
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reg |= DSU_CLUSTER_PWR_OFF;
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write_clusterpwrdn(reg);
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#endif
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}
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}
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/*******************************************************************************
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