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SPMC: manifest changes to support multicore boot 

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Icf90c2ccce75257908ba3d4703926041d64b1dd3
This commit is contained in:
Olivier Deprez 2020-06-12 18:10:28 +02:00 committed by Max Shvetsov
parent a92bc73b8e
commit 2111b0024c
2 changed files with 19 additions and 17 deletions
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2
include/services/spm_core_manifest.h
View File

@ -44,7 +44,7 @@ typedef struct spm_core_manifest_sect_attribute {
uint32_t binary_size;
/*
* ID of the SPMD (mandatory)
* ID of the SPMC (mandatory)
*/
uint16_t spmc_id;

34
plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
View File

@ -5,6 +5,14 @@
*/
/dts-v1/;
#define AFF 00
#include "fvp-defs.dtsi"
#undef POST
#define POST \
enable-method = "psci"; \
};
/ {
compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>;
@ -17,6 +25,7 @@
exec_state = <0x0>;
load_address = <0x0 0x6000000>;
entrypoint = <0x0 0x6000000>;
binary_size = <0x80000>;
};
chosen {
@ -51,22 +60,15 @@
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu-map {
cluster0 {
core0 {
cpu = <0x2>;
};
};
};
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <0xc>;
phandle = <0x2>;
};
CPU_0
/* SPM(Hafnium) requires secondary cpu nodes are declared in descending order */
CPU_7
CPU_6
CPU_5
CPU_4
CPU_3
CPU_2
CPU_1
};
memory@60000000 {