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fix(stm32mp1): do not reopen debug features 

On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewrite this
register. This part of code is just removed.
An INFO message is displayed if debug is disabled.
The freeze of the watchdog during debug is also removed.
In case of debug, this must be managed by the software that enables
the debugger.

Change-Id: I19fbd3c487bb1018db30fd599cfa94fe5090899f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This commit is contained in:
Yann Gautier 2021-09-15 14:49:48 +02:00 committed by Yann Gautier
parent a24d5947af
commit 21cfa4531a
3 changed files with 4 additions and 51 deletions
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6
plat/st/stm32mp1/bl2_plat_setup.c
View File

@ -159,7 +159,6 @@ void bl2_platform_setup(void)
void bl2_el3_plat_arch_setup(void)
{
int32_t result;
const char *board_model;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
@ -293,11 +292,6 @@ skip_console_init:
stm32_iwdg_refresh();
result = stm32mp1_dbgmcu_freeze_iwdg2();
if (result != 0) {
INFO("IWDG2 freeze error : %i\n", result);
}
stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
stm32mp1_auth_ops.verify_signature =
boot_context->bootrom_ecdsa_verify_signature;

9
plat/st/stm32mp1/include/stm32mp1_dbgmcu.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2015-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,11 +13,4 @@
int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version);
int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id);
/*
* Freeze watchdog when a debugger is attached, if the security configuration
* allows it.
* Return 0 on success, a negative error value otherwise.
*/
int stm32mp1_dbgmcu_freeze_iwdg2(void);
#endif /* STM32MP1_DBGMCU_H */

40
plat/st/stm32mp1/stm32mp1_dbgmcu.c
View File

@ -18,28 +18,16 @@
#include <stm32mp1_dbgmcu.h>
#define DBGMCU_IDC U(0x00)
#define DBGMCU_APB4FZ1 U(0x2C)
#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
#define DBGMCU_IDC_REV_ID_SHIFT 16
#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
static int stm32mp1_dbgmcu_init(void)
{
uint32_t dbg_conf;
dbg_conf = bsec_read_debug_conf();
if ((dbg_conf & BSEC_DBGSWGEN) == 0U) {
uint32_t result = bsec_write_debug_conf(dbg_conf |
BSEC_DBGSWGEN);
if (result != BSEC_OK) {
ERROR("Error enabling DBGSWGEN\n");
return -1;
}
if ((bsec_read_debug_conf() & BSEC_DBGSWGEN) == 0U) {
INFO("Software access to all debug components is disabled\n");
return -1;
}
mmio_setbits_32(RCC_BASE + RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
@ -84,25 +72,3 @@ int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id)
return 0;
}
/*
* @brief Freeze IWDG2 in debug mode.
* @retval None.
*/
int stm32mp1_dbgmcu_freeze_iwdg2(void)
{
uint32_t dbg_conf;
if (stm32mp1_dbgmcu_init() != 0) {
return -EPERM;
}
dbg_conf = bsec_read_debug_conf();
if ((dbg_conf & (BSEC_SPIDEN | BSEC_SPINDEN)) != 0U) {
mmio_setbits_32(DBGMCU_BASE + DBGMCU_APB4FZ1,
DBGMCU_APB4FZ1_IWDG2);
}
return 0;
}