Merge "imx: Unify Platform specific defines for PSCI module" into integration
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commit
22d7dd7fc7
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@ -13,15 +13,15 @@
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define PICOPI_PRIMARY_CPU 0
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#define PICOPI_PRIMARY_CPU U(0)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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@ -13,15 +13,15 @@
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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PLATFORM_CLUSTER1_CORE_COUNT)
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PLATFORM_CLUSTER1_CORE_COUNT)
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#define WARP7_PRIMARY_CPU 0
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#define WARP7_PRIMARY_CPU U(0)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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PLATFORM_CORE_COUNT)
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@ -10,11 +10,11 @@
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#define PLATFORM_STACK_SIZE 0xB00
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#define PLATFORM_STACK_SIZE 0xB00
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#define CACHE_WRITEBACK_GRANULE 64
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#define CACHE_WRITEBACK_GRANULE 64
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#define PLAT_PRIMARY_CPU 0x0
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#define PLAT_PRIMARY_CPU U(0x0)
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#define PLATFORM_MAX_CPU_PER_CLUSTER 4
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#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define IMX_PWR_LVL0 MPIDR_AFFLVL0
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#define IMX_PWR_LVL0 MPIDR_AFFLVL0
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#define PLATFORM_STACK_SIZE 0x800
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#define PLATFORM_STACK_SIZE 0x800
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#define CACHE_WRITEBACK_GRANULE 64
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#define CACHE_WRITEBACK_GRANULE 64
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#define PLAT_PRIMARY_CPU 0x0
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#define PLAT_PRIMARY_CPU U(0x0)
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#define PLATFORM_MAX_CPU_PER_CLUSTER 4
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#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define IMX_PWR_LVL0 MPIDR_AFFLVL0
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#define IMX_PWR_LVL0 MPIDR_AFFLVL0
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define PLATFORM_STACK_SIZE 0X400
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#define PLATFORM_STACK_SIZE 0X400
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#define CACHE_WRITEBACK_GRANULE 64
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#define CACHE_WRITEBACK_GRANULE 64
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#define PLAT_PRIMARY_CPU 0x0
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#define PLAT_PRIMARY_CPU U(0x0)
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#define PLATFORM_MAX_CPU_PER_CLUSTER 4
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#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT 2
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#define PLATFORM_CLUSTER1_CORE_COUNT U(2)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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PLATFORM_CLUSTER1_CORE_COUNT)
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PLATFORM_CLUSTER1_CORE_COUNT)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -15,12 +15,12 @@
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#define PLATFORM_STACK_SIZE 0x400
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#define PLATFORM_STACK_SIZE 0x400
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#define CACHE_WRITEBACK_GRANULE 64
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#define CACHE_WRITEBACK_GRANULE 64
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#define PLAT_PRIMARY_CPU 0x0
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#define PLAT_PRIMARY_CPU U(0x0)
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#define PLATFORM_MAX_CPU_PER_CLUSTER 4
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#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CORE_COUNT 4
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#define PLATFORM_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PWR_DOMAIN_AT_MAX_LVL U(1)
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#define PWR_DOMAIN_AT_MAX_LVL U(1)
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_PWR_LVL U(2)
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