Merge "imx: Unify Platform specific defines for PSCI module" into integration

This commit is contained in:
Soby Mathew 2020-01-24 13:14:22 +00:00 committed by TrustedFirmware Code Review
commit 22d7dd7fc7
6 changed files with 31 additions and 31 deletions

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@ -13,15 +13,15 @@
#define PLATFORM_STACK_SIZE 0x1000 #define PLATFORM_STACK_SIZE 0x1000
#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
#define PLATFORM_CLUSTER_COUNT 1 #define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
#define PICOPI_PRIMARY_CPU 0 #define PICOPI_PRIMARY_CPU U(0)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT) PLATFORM_CORE_COUNT)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1

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@ -13,15 +13,15 @@
#define PLATFORM_STACK_SIZE 0x1000 #define PLATFORM_STACK_SIZE 0x1000
#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
#define PLATFORM_CLUSTER_COUNT 1 #define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CLUSTER1_CORE_COUNT 0 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
PLATFORM_CLUSTER1_CORE_COUNT) PLATFORM_CLUSTER1_CORE_COUNT)
#define WARP7_PRIMARY_CPU 0 #define WARP7_PRIMARY_CPU U(0)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT) PLATFORM_CORE_COUNT)

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@ -10,11 +10,11 @@
#define PLATFORM_STACK_SIZE 0xB00 #define PLATFORM_STACK_SIZE 0xB00
#define CACHE_WRITEBACK_GRANULE 64 #define CACHE_WRITEBACK_GRANULE 64
#define PLAT_PRIMARY_CPU 0x0 #define PLAT_PRIMARY_CPU U(0x0)
#define PLATFORM_MAX_CPU_PER_CLUSTER 4 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
#define PLATFORM_CLUSTER_COUNT 1 #define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CLUSTER0_CORE_COUNT 4 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT 0 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
#define IMX_PWR_LVL0 MPIDR_AFFLVL0 #define IMX_PWR_LVL0 MPIDR_AFFLVL0

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@ -10,11 +10,11 @@
#define PLATFORM_STACK_SIZE 0x800 #define PLATFORM_STACK_SIZE 0x800
#define CACHE_WRITEBACK_GRANULE 64 #define CACHE_WRITEBACK_GRANULE 64
#define PLAT_PRIMARY_CPU 0x0 #define PLAT_PRIMARY_CPU U(0x0)
#define PLATFORM_MAX_CPU_PER_CLUSTER 4 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
#define PLATFORM_CLUSTER_COUNT 1 #define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CLUSTER0_CORE_COUNT 4 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT 0 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
#define IMX_PWR_LVL0 MPIDR_AFFLVL0 #define IMX_PWR_LVL0 MPIDR_AFFLVL0

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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -15,11 +15,11 @@
#define PLATFORM_STACK_SIZE 0X400 #define PLATFORM_STACK_SIZE 0X400
#define CACHE_WRITEBACK_GRANULE 64 #define CACHE_WRITEBACK_GRANULE 64
#define PLAT_PRIMARY_CPU 0x0 #define PLAT_PRIMARY_CPU U(0x0)
#define PLATFORM_MAX_CPU_PER_CLUSTER 4 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
#define PLATFORM_CLUSTER_COUNT 2 #define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CLUSTER0_CORE_COUNT 4 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT 2 #define PLATFORM_CLUSTER1_CORE_COUNT U(2)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
PLATFORM_CLUSTER1_CORE_COUNT) PLATFORM_CLUSTER1_CORE_COUNT)

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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -15,12 +15,12 @@
#define PLATFORM_STACK_SIZE 0x400 #define PLATFORM_STACK_SIZE 0x400
#define CACHE_WRITEBACK_GRANULE 64 #define CACHE_WRITEBACK_GRANULE 64
#define PLAT_PRIMARY_CPU 0x0 #define PLAT_PRIMARY_CPU U(0x0)
#define PLATFORM_MAX_CPU_PER_CLUSTER 4 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
#define PLATFORM_CLUSTER_COUNT 1 #define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CORE_COUNT 4 #define PLATFORM_CORE_COUNT U(4)
#define PLATFORM_CLUSTER0_CORE_COUNT 4 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT 0 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
#define PWR_DOMAIN_AT_MAX_LVL U(1) #define PWR_DOMAIN_AT_MAX_LVL U(1)
#define PLAT_MAX_PWR_LVL U(2) #define PLAT_MAX_PWR_LVL U(2)