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refactor(stm32mp1): remove the support of calibration result 

The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.

The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.

This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
  the optional "st,phy-cal"

After this patch the built-in calibration is always executed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
This commit is contained in:
Patrick Delaunay 2021-04-30 17:31:52 +02:00 committed by Yann Gautier
parent a078134e23
commit 26cf5cf6d6
6 changed files with 4 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/st/ddr/stm32mp1_ddr.c
View File

@ -154,22 +154,6 @@ static const struct reg_desc ddrphy_timing[] = {
DDRPHY_REG_TIMING(mr3),
};
#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
static const struct reg_desc ddrphy_cal[] = {
DDRPHY_REG_CAL(dx0dllcr),
DDRPHY_REG_CAL(dx0dqtr),
DDRPHY_REG_CAL(dx0dqstr),
DDRPHY_REG_CAL(dx1dllcr),
DDRPHY_REG_CAL(dx1dqtr),
DDRPHY_REG_CAL(dx1dqstr),
DDRPHY_REG_CAL(dx2dllcr),
DDRPHY_REG_CAL(dx2dqtr),
DDRPHY_REG_CAL(dx2dqstr),
DDRPHY_REG_CAL(dx3dllcr),
DDRPHY_REG_CAL(dx3dqtr),
DDRPHY_REG_CAL(dx3dqstr),
};
#define DDR_REG_DYN(x) \
{ \
.name = #x, \
@ -207,7 +191,6 @@ enum reg_type {
REG_MAP,
REGPHY_REG,
REGPHY_TIMING,
REGPHY_CAL,
/*
* Dynamic registers => managed in driver or not changed,
* can be dumped in interactive mode.
@ -267,12 +250,6 @@ static const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
.size = ARRAY_SIZE(ddrphy_timing),
.base = DDRPHY_BASE
},
[REGPHY_CAL] = {
.name = "cal",
.desc = ddrphy_cal,
.size = ARRAY_SIZE(ddrphy_cal),
.base = DDRPHY_BASE
},
[REG_DYN] = {
.name = "dyn",
.desc = ddr_dyn,
@ -812,7 +789,6 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
*/
set_reg(priv, REGPHY_REG, &config->p_reg);
set_reg(priv, REGPHY_TIMING, &config->p_timing);
set_reg(priv, REGPHY_CAL, &config->p_cal);
/* DDR3 = don't set DLLOFF for init mode */
if ((config->c_reg.mstr &

1
drivers/st/ddr/stm32mp1_ram.c
View File

@ -193,7 +193,6 @@ static int stm32mp1_ddr_setup(void)
CTL_PARAM(perf),
PHY_PARAM(reg),
PHY_PARAM(timing),
PHY_PARAM(cal)
};
if (fdt_get_address(&fdt) == 0) {

17
fdts/stm32mp15-ddr.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
*/
&ddr {
@ -109,19 +109,4 @@
DDR_MR2
DDR_MR3
>;
st,phy-cal = <
DDR_DX0DLLCR
DDR_DX0DQTR
DDR_DX0DQSTR
DDR_DX1DLLCR
DDR_DX1DQTR
DDR_DX1DQSTR
DDR_DX2DLLCR
DDR_DX2DQTR
DDR_DX2DQSTR
DDR_DX3DLLCR
DDR_DX3DQTR
DDR_DX3DQSTR
>;
};

14
fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved
*/
/*
@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

14
fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved
*/
/*
@ -100,20 +100,8 @@
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

18
include/drivers/st/stm32mp1_ddr.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -136,21 +136,6 @@ struct stm32mp1_ddrphy_timing {
uint32_t mr3;
};
struct stm32mp1_ddrphy_cal {
uint32_t dx0dllcr;
uint32_t dx0dqtr;
uint32_t dx0dqstr;
uint32_t dx1dllcr;
uint32_t dx1dqtr;
uint32_t dx1dqstr;
uint32_t dx2dllcr;
uint32_t dx2dqtr;
uint32_t dx2dqstr;
uint32_t dx3dllcr;
uint32_t dx3dqtr;
uint32_t dx3dqstr;
};
struct stm32mp1_ddr_info {
const char *name;
uint32_t speed; /* in kHZ */
@ -165,7 +150,6 @@ struct stm32mp1_ddr_config {
struct stm32mp1_ddrctrl_perf c_perf;
struct stm32mp1_ddrphy_reg p_reg;
struct stm32mp1_ddrphy_timing p_timing;
struct stm32mp1_ddrphy_cal p_cal;
};
int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed);