andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

zynqmp: pm: Fix model of ACPU clocks 

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
This commit is contained in:
Jolly Shah 2019-01-02 13:45:53 -08:00
parent b6c56bdb0c
commit 284b2f095b
2 changed files with 26 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View File

@ -330,18 +330,6 @@ static struct pm_clock_node acpu_nodes[] = {
.mult = NA_MULT,
.div = NA_DIV,
},
{
.type = TYPE_GATE,
.offset = PERIPH_GATE_SHIFT,
.width = PERIPH_GATE_WIDTH,
.clkflags = CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED |
CLK_IS_BASIC |
CLK_IS_CRITICAL,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
};
static struct pm_clock_node generic_mux_div_nodes[] = {
@ -476,6 +464,20 @@ static struct pm_clock_node acpu_half_nodes[] = {
},
};
static struct pm_clock_node acpu_full_nodes[] = {
{
.type = TYPE_GATE,
.offset = 24,
.width = PERIPH_GATE_WIDTH,
.clkflags = CLK_IGNORE_UNUSED |
CLK_SET_RATE_PARENT |
CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
},
};
static struct pm_clock_node wdt_nodes[] = {
{
.type = TYPE_MUX,
@ -1205,6 +1207,17 @@ static struct pm_clock clocks[] = {
.nodes = &acpu_nodes,
.num_nodes = ARRAY_SIZE(acpu_nodes),
},
[CLK_ACPU_FULL] = {
.name = "acpu_full",
.control_reg = CRF_APB_ACPU_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_ACPU | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
CLK_NA_PARENT
}),
.nodes = &acpu_full_nodes,
.num_nodes = ARRAY_SIZE(acpu_full_nodes),
},
[CLK_DBG_TRACE] = {
.name = "dbg_trace",
.control_reg = CRF_APB_DBG_TRACE_CTRL,

1
plat/xilinx/zynqmp/pm_service/pm_api_clock.h
View File

@ -159,6 +159,7 @@ enum clock_id {
CLK_VPLL_POST_SRC,
CLK_CAN0_MIO,
CLK_CAN1_MIO,
CLK_ACPU_FULL,
END_OF_OUTPUT_CLKS,
};