zynqmp: pm: Fix model of ACPU clocks
In the existing model for ACPU clock the mux, divider, and gate were represented as one clock and ACPU_HALF was modelled as child of ACPU clock. This is not correct. ACPU clock model contains only mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF clocks which have only gates. The models of ACPU and ACPU_HALF clocks are fixed and ACPU_FULL clock is added. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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@ -330,18 +330,6 @@ static struct pm_clock_node acpu_nodes[] = {
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.mult = NA_MULT,
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.mult = NA_MULT,
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.div = NA_DIV,
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.div = NA_DIV,
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},
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},
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{
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.type = TYPE_GATE,
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.offset = PERIPH_GATE_SHIFT,
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.width = PERIPH_GATE_WIDTH,
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.clkflags = CLK_SET_RATE_PARENT |
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CLK_IGNORE_UNUSED |
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CLK_IS_BASIC |
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CLK_IS_CRITICAL,
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.typeflags = NA_TYPE_FLAGS,
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.mult = NA_MULT,
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.div = NA_DIV,
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},
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};
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};
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static struct pm_clock_node generic_mux_div_nodes[] = {
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static struct pm_clock_node generic_mux_div_nodes[] = {
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@ -476,6 +464,20 @@ static struct pm_clock_node acpu_half_nodes[] = {
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},
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},
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};
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};
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static struct pm_clock_node acpu_full_nodes[] = {
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{
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.type = TYPE_GATE,
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.offset = 24,
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.width = PERIPH_GATE_WIDTH,
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.clkflags = CLK_IGNORE_UNUSED |
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CLK_SET_RATE_PARENT |
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CLK_IS_BASIC,
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.typeflags = NA_TYPE_FLAGS,
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.mult = NA_MULT,
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.div = NA_DIV,
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},
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};
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static struct pm_clock_node wdt_nodes[] = {
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static struct pm_clock_node wdt_nodes[] = {
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{
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{
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.type = TYPE_MUX,
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.type = TYPE_MUX,
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@ -1205,6 +1207,17 @@ static struct pm_clock clocks[] = {
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.nodes = &acpu_nodes,
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.nodes = &acpu_nodes,
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.num_nodes = ARRAY_SIZE(acpu_nodes),
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.num_nodes = ARRAY_SIZE(acpu_nodes),
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},
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},
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[CLK_ACPU_FULL] = {
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.name = "acpu_full",
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.control_reg = CRF_APB_ACPU_CTRL,
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.status_reg = 0,
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.parents = &((int32_t []) {
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CLK_ACPU | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
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CLK_NA_PARENT
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}),
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.nodes = &acpu_full_nodes,
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.num_nodes = ARRAY_SIZE(acpu_full_nodes),
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},
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[CLK_DBG_TRACE] = {
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[CLK_DBG_TRACE] = {
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.name = "dbg_trace",
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.name = "dbg_trace",
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.control_reg = CRF_APB_DBG_TRACE_CTRL,
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.control_reg = CRF_APB_DBG_TRACE_CTRL,
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@ -159,6 +159,7 @@ enum clock_id {
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CLK_VPLL_POST_SRC,
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CLK_VPLL_POST_SRC,
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CLK_CAN0_MIO,
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CLK_CAN0_MIO,
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CLK_CAN1_MIO,
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CLK_CAN1_MIO,
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CLK_ACPU_FULL,
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END_OF_OUTPUT_CLKS,
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END_OF_OUTPUT_CLKS,
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};
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};
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