feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access by device apc. Add clock and pll related SiP call for the access from Kernel space. Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
This commit is contained in:
Flora Fu
parent
88906b4437
commit
296b590206
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@ -0,0 +1,581 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/spinlock.h>
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#include <apupwr_clkctl.h>
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#include <apupwr_clkctl_def.h>
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#include <mtk_plat_common.h>
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#include <platform_def.h>
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uint32_t mixed_con0_addr[APUPLL_MAX] = {
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APU_PLL4H_PLL1_CON0,
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APU_PLL4H_PLL2_CON0,
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APU_PLL4H_PLL3_CON0,
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APU_PLL4H_PLL4_CON0,
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};
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uint32_t mixed_con1_addr[APUPLL_MAX] = {
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APU_PLL4H_PLL1_CON1,
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APU_PLL4H_PLL2_CON1,
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APU_PLL4H_PLL3_CON1,
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APU_PLL4H_PLL4_CON1,
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};
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uint32_t mixed_con3_addr[APUPLL_MAX] = {
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APU_PLL4H_PLL1_CON3,
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APU_PLL4H_PLL2_CON3,
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APU_PLL4H_PLL3_CON3,
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APU_PLL4H_PLL4_CON3,
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};
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uint32_t fhctl_dds_addr[APUPLL_MAX] = {
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APU_PLL4H_FHCTL0_DDS,
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APU_PLL4H_FHCTL1_DDS,
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APU_PLL4H_FHCTL2_DDS,
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APU_PLL4H_FHCTL3_DDS,
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};
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uint32_t fhctl_dvfs_addr[APUPLL_MAX] = {
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APU_PLL4H_FHCTL0_DVFS,
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APU_PLL4H_FHCTL1_DVFS,
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APU_PLL4H_FHCTL2_DVFS,
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APU_PLL4H_FHCTL3_DVFS,
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};
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uint32_t fhctl_mon_addr[APUPLL_MAX] = {
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APU_PLL4H_FHCTL0_MON,
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APU_PLL4H_FHCTL1_MON,
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APU_PLL4H_FHCTL2_MON,
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APU_PLL4H_FHCTL3_MON,
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};
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uint32_t fhctl_cfg_addr[APUPLL_MAX] = {
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APU_PLL4H_FHCTL0_CFG,
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APU_PLL4H_FHCTL1_CFG,
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APU_PLL4H_FHCTL2_CFG,
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APU_PLL4H_FHCTL3_CFG,
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};
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static spinlock_t apupll_lock;
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static spinlock_t npupll_lock;
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static spinlock_t apupll_1_lock;
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static spinlock_t apupll_2_lock;
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static uint32_t pll_cnt[APUPLL_MAX];
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/**
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* vd2pllidx() - voltage domain to pll idx.
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* @domain: the voltage domain for getting pll index.
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*
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* Caller will get correspond pll index by different voltage domain.
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* pll_idx[0] --> APUPLL (MDLA0/1)
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* pll_idx[1] --> NPUPLL (VPU0/1)
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* pll_idx[2] --> APUPLL1(CONN)
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* pll_idx[3] --> APUPLL2(IOMMU)
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* The longer description may have multiple paragraphs.
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*
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* Context: Any context.
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* Return:
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* * 0 ~ 3 - return the corresponding pll index
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* * -EEXIST - cannot find pll idex of the specific voltage domain
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*
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*/
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static int32_t vd2pllidx(enum dvfs_voltage_domain domain)
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{
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int32_t ret;
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switch (domain) {
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case V_VPU0:
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case V_VPU1:
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ret = NPUPLL;
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break;
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case V_MDLA0:
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case V_MDLA1:
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ret = APUPLL;
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break;
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case V_TOP_IOMMU:
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ret = APUPLL2;
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break;
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case V_APU_CONN:
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ret = APUPLL1;
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break;
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default:
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ERROR("%s wrong voltage domain: %d\n", __func__, domain);
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ret = -EEXIST; /* non-exist */
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break;
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}
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return ret;
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}
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/**
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* pllidx2name() - return names of specific pll index.
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* @pll_idx: input for specific pll index.
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*
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* Given pll index, this function will return name of it.
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*
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* Context: Any context.
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* Return: Names of pll_idx, if found, otherwise will return "NULL"
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*/
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static const char *pllidx2name(int32_t pll_idx)
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{
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static const char *const names[] = {
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[APUPLL] = "PLL4H_PLL1",
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[NPUPLL] = "PLL4H_PLL2",
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[APUPLL1] = "PLL4H_PLL3",
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[APUPLL2] = "PLL4H_PLL4",
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[APUPLL_MAX] = "NULL",
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};
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if (pll_idx >= APUPLL_MAX) {
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pll_idx = APUPLL_MAX;
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}
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return names[pll_idx];
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}
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/**
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* _fhctl_mon_done() - poll whether fhctl HW mode is done.
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* @pll_idx: input for specific pll index.
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* @tar_dds: target dds for fhctl_mon to be.
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*
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* Given pll index, this function will continue to poll whether fhctl_mon
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* has reached the expected value within 80us.
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*
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* Context: Any context.
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* Return:
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* * 0 - OK for fhctl_mon == tar_dds
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* * -ETIMEDOUT - fhctl_mon not reach tar_dds
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*/
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static int32_t _fhctl_mon_done(uint32_t pll_idx, unsigned long tar_dds)
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{
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unsigned long mon_dds;
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uint64_t timeout = timeout_init_us(PLL_READY_TIME_20US);
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int32_t ret = 0;
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tar_dds &= DDS_MASK;
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do {
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mon_dds = apupwr_readl(fhctl_mon_addr[pll_idx]) & DDS_MASK;
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if (mon_dds == tar_dds) {
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break;
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}
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if (timeout_elapsed(timeout)) {
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ERROR("%s monitor DDS 0x%08lx != expect 0x%08lx\n",
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pllidx2name(pll_idx), mon_dds, tar_dds);
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ret = -ETIMEDOUT;
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break;
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}
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} while (mon_dds != tar_dds);
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return ret;
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}
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/**
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* _pll_get_postdiv_reg() - return current post dividor of pll_idx
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* @pll_idx: input for specific pll index.
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*
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* Given pll index, this function will return its current post dividor.
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*
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* Context: Any context.
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* Return: post dividor of current pll_idx.
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*
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*/
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static uint32_t _pll_get_postdiv_reg(uint32_t pll_idx)
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{
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int32_t pll_postdiv_reg = 0;
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uint32_t val;
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val = apupwr_readl(mixed_con1_addr[pll_idx]);
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pll_postdiv_reg = (val >> POSDIV_SHIFT) & POSDIV_MASK;
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return pll_postdiv_reg;
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}
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/**
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* _set_postdiv_reg() - set pll_idx's post dividor.
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* @pll_idx: Which PLL to enable/disable
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* @post_div: the register value of post dividor to be wrtten.
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*
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* Below are lists of post dividor register value and its meaning:
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* [31] APUPLL_SDM_PCW_CHG
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* [26:24] APUPLL_POSDIV
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* [21:0] APUPLL_SDM_PCW (8bit integer + 14bit fraction)
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* expected freq range ----- divider-------post divider in reg:
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* >1500M (1500/ 1) -> 1 -> 0(2 to the zero power)
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* > 750M (1500/ 2) -> 2 -> 1(2 to the 1st power)
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* > 375M (1500/ 4) -> 4 -> 2(2 to the 2nd power)
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* > 187.5M (1500/ 8) -> 8 -> 3(2 to the 3rd power)
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* > 93.75M (1500/16) -> 16 -> 4(2 to the 4th power)
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*
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* Context: Any context.
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*/
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static void _set_postdiv_reg(uint32_t pll_idx, uint32_t post_div)
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{
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apupwr_clrbits(POSDIV_MASK << POSDIV_SHIFT, mixed_con1_addr[pll_idx]);
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apupwr_setbits((post_div & POSDIV_MASK) << POSDIV_SHIFT,
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mixed_con1_addr[pll_idx]);
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}
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/**
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* _cal_pll_data() - input freq, calculate correspond post dividor and dds.
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* @pd: address of output post dividor.
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* @dds: address of output dds.
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* @freq: input frequency.
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*
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* Given freq, this function will calculate correspond post dividor and dds.
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*
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* Context: Any context.
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* Return:
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* * 0 - done for calculating post dividor and dds.
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*/
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static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq)
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{
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uint32_t vco, postdiv_val = 1, postdiv_reg = 0;
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uint32_t pcw_val;
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vco = freq;
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postdiv_val = 1;
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postdiv_reg = 0;
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while (vco <= FREQ_VCO_MIN) {
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postdiv_val = postdiv_val << 1;
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postdiv_reg = postdiv_reg + 1;
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vco = vco << 1;
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}
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pcw_val = vco * (1 << PCW_FRACTIONAL_SHIFT);
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pcw_val = pcw_val / FREQ_FIN;
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if (postdiv_reg == 0) { /* Fvco * 2 with post_divider = 2 */
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pcw_val = pcw_val * 2;
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postdiv_val = postdiv_val << 1;
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postdiv_reg = postdiv_reg + 1;
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} /* Post divider is 1 is not available */
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*pd = postdiv_reg;
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*dds = pcw_val | RG_PLL_SDM_PCW_CHG;
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return 0;
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}
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/**
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* _pll_en() - enable/disable RG_PLL_EN of CON1 for pll[pll_idx]
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* @pll_idx: Which PLL to enable/disable
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* @on: 1 -> enable, 0 -> disable.
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*
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* This funciton will only change RG_PLL_EN of CON1 for pll[pll_idx].
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*
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* Context: Any context.
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*/
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static void _pll_en(uint32_t pll_idx, bool on)
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{
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if (on) {
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apupwr_setbits(RG_PLL_EN, mixed_con0_addr[pll_idx]);
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} else {
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apupwr_clrbits(RG_PLL_EN, mixed_con0_addr[pll_idx]);
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}
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}
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/**
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* _pll_pwr() - enable/disable PLL_SDM_PWR_ON of CON3 for pll[pll_idx]
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* @pll_idx: Which PLL to enable/disable
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* @on: 1 -> enable, 0 -> disable.
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*
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* This funciton will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
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*
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* Context: Any context.
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*/
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static void _pll_pwr(uint32_t pll_idx, bool on)
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{
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if (on) {
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apupwr_setbits(DA_PLL_SDM_PWR_ON, mixed_con3_addr[pll_idx]);
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} else {
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apupwr_clrbits(DA_PLL_SDM_PWR_ON, mixed_con3_addr[pll_idx]);
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}
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}
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/**
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* _pll_iso() - enable/disable PLL_SDM_ISO_EN of CON3 for pll[pll_idx]
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* @pll_idx: Which PLL to enable/disable
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* @enable: 1 -> turn on isolation, 0 -> turn off isolation.
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*
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* This funciton will turn on/off pll isolation by
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* changing PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
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*
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* Context: Any context.
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*/
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static void _pll_iso(uint32_t pll_idx, bool enable)
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{
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if (enable) {
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apupwr_setbits(DA_PLL_SDM_ISO_EN, mixed_con3_addr[pll_idx]);
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} else {
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apupwr_clrbits(DA_PLL_SDM_ISO_EN, mixed_con3_addr[pll_idx]);
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}
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}
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/**
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* _pll_switch() - entry point to turn whole PLL on/off
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* @pll_idx: Which PLL to enable/disable
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* @on: 1 -> enable, 0 -> disable.
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* @fhctl_en: enable or disable fhctl function
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*
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* This is the entry poing for controlling pll and fhctl funciton on/off.
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* Caller can chose only enable pll instead of fhctl function.
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*
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* Context: Any context.
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* Return:
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* * 0 - done for enable pll or fhctl as well.
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*/
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static int32_t _pll_switch(uint32_t pll_idx, bool on, bool fhctl_en)
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{
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int32_t ret = 0;
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if (pll_idx >= APUPLL_MAX) {
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ERROR("%s wrong pll_idx: %d\n", __func__, pll_idx);
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ret = -EINVAL;
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goto err;
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}
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if (on) {
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_pll_pwr(pll_idx, true);
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udelay(PLL_CMD_READY_TIME_1US);
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_pll_iso(pll_idx, false);
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udelay(PLL_CMD_READY_TIME_1US);
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_pll_en(pll_idx, true);
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udelay(PLL_READY_TIME_20US);
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} else {
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_pll_en(pll_idx, false);
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_pll_iso(pll_idx, true);
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_pll_pwr(pll_idx, false);
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}
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err:
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return ret;
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}
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/**
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* apu_pll_enable() - API for smc function to enable/disable pll
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* @pll_idx: Which pll to enable/disable.
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* @enable: 1 -> enable, 0 -> disable.
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* @fhctl_en: enable or disable fhctl function
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*
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* pll_idx[0] --> APUPLL (MDLA0/1)
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* pll_idx[1] --> NPUPLL (VPU0/1)
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* pll_idx[2] --> APUPLL1(CONN)
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* pll_idx[3] --> APUPLL2(IOMMU)
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* The differences between _pll_switch are:
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* 1. Atomic update pll reference cnt to protect double enable pll &
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* close pll during user is not zero.
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*
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* Context: Any context.
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* Return:
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* * 0 - done for enable pll or fhctl as well.
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*/
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int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en)
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{
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int32_t ret = 0;
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if (pll_idx >= APUPLL_MAX) {
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ERROR("%s wrong pll_idx: %d\n", __func__, pll_idx);
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ret = -EINVAL;
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goto err;
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}
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if (enable) {
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switch (pll_idx) {
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case APUPLL:
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spin_lock(&apupll_lock);
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if (pll_cnt[APUPLL] == 0) {
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_pll_switch(pll_idx, enable, fhctl_en);
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}
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pll_cnt[APUPLL]++;
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spin_unlock(&apupll_lock);
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break;
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case NPUPLL:
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spin_lock(&npupll_lock);
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if (pll_cnt[NPUPLL] == 0) {
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_pll_switch(pll_idx, enable, fhctl_en);
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}
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pll_cnt[NPUPLL]++;
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spin_unlock(&npupll_lock);
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break;
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case APUPLL1:
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spin_lock(&apupll_1_lock);
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if (pll_cnt[APUPLL1] == 0) {
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_pll_switch(pll_idx, enable, fhctl_en);
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}
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pll_cnt[APUPLL1]++;
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spin_unlock(&apupll_1_lock);
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break;
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case APUPLL2:
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spin_lock(&apupll_2_lock);
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if (pll_cnt[APUPLL2] == 0) {
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_pll_switch(pll_idx, enable, fhctl_en);
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}
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pll_cnt[APUPLL2]++;
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spin_unlock(&apupll_2_lock);
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break;
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default:
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ERROR("%s invalid pll_idx: %d\n", __func__, pll_idx);
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ret = -EINVAL;
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break;
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}
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} else {
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switch (pll_idx) {
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case APUPLL:
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spin_lock(&apupll_lock);
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if (pll_cnt[APUPLL]) {
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pll_cnt[APUPLL]--;
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}
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if (pll_cnt[APUPLL] == 0) {
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_pll_switch(pll_idx, enable, fhctl_en);
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}
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spin_unlock(&apupll_lock);
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break;
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case NPUPLL:
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spin_lock(&npupll_lock);
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if (pll_cnt[NPUPLL]) {
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pll_cnt[NPUPLL]--;
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}
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if (pll_cnt[NPUPLL] == 0) {
|
||||
_pll_switch(pll_idx, enable, fhctl_en);
|
||||
}
|
||||
spin_unlock(&npupll_lock);
|
||||
break;
|
||||
case APUPLL1:
|
||||
spin_lock(&apupll_1_lock);
|
||||
if (pll_cnt[APUPLL1]) {
|
||||
pll_cnt[APUPLL1]--;
|
||||
}
|
||||
if (pll_cnt[APUPLL1] == 0) {
|
||||
_pll_switch(pll_idx, enable, fhctl_en);
|
||||
}
|
||||
spin_unlock(&apupll_1_lock);
|
||||
break;
|
||||
case APUPLL2:
|
||||
spin_lock(&apupll_2_lock);
|
||||
if (pll_cnt[APUPLL2]) {
|
||||
pll_cnt[APUPLL2]--;
|
||||
}
|
||||
if (pll_cnt[APUPLL2] == 0) {
|
||||
_pll_switch(pll_idx, enable, fhctl_en);
|
||||
}
|
||||
spin_unlock(&apupll_2_lock);
|
||||
break;
|
||||
default:
|
||||
ERROR("%s invalid pll_idx: %d\n", __func__, pll_idx);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* anpu_pll_set_rate() - API for smc function to set rate of voltage domain.
|
||||
* @domain: Which pll of correspond voltage domain to change rate.
|
||||
* @mode: which mode to use when set_rate
|
||||
* @freq: which frequency to set.
|
||||
*
|
||||
* For V_VPU0/1, it will only allow 1 of them to modify NPUPLL
|
||||
* such that there will be no race condition happen.
|
||||
*
|
||||
* For V_MDLA0/1, it will only allow 1 of them to modify APUPLL1
|
||||
* such that there will be no race condition happen.
|
||||
*
|
||||
* There are 3 kinds of modes to set pll's rate.
|
||||
* 1. pure sw mode: (CON0_PCW)
|
||||
* fhctl function is off and change rate by programming CON1_PCW.
|
||||
* 2. fhctl sw mode: (FHCTL_SW)
|
||||
* fhctl function is on and change rate by programming fhctl_dds.
|
||||
* (post dividor is still need to program CON1_PCW)
|
||||
* 3. fhctl hw mode: (FHCTL_HW)
|
||||
* fhctl function is on and change rate by programming fhctl_dvfs.
|
||||
* (post dividor is still need to program CON1_PCW)
|
||||
*
|
||||
* Context: Any context.
|
||||
* Return:
|
||||
* * 0 - done for set rate of voltage domain.
|
||||
*/
|
||||
int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
|
||||
enum pll_set_rate_mode mode, int32_t freq)
|
||||
{
|
||||
uint32_t pd, old_pd, dds;
|
||||
int32_t pll_idx, ret = 0;
|
||||
|
||||
pll_idx = vd2pllidx(domain);
|
||||
if (pll_idx < 0) {
|
||||
ret = pll_idx;
|
||||
goto err;
|
||||
}
|
||||
|
||||
_cal_pll_data(&pd, &dds, freq / 1000);
|
||||
|
||||
INFO("%s %s new post_div=%d, target dds=0x%08x(%dMhz) mode = %d\n",
|
||||
__func__, pllidx2name(pll_idx), pd, dds, freq / 1000, mode);
|
||||
|
||||
/* spin_lock for NPULL, since vpu0/1 share npupll */
|
||||
if (domain == V_VPU0 || domain == V_VPU1) {
|
||||
spin_lock(&npupll_lock);
|
||||
}
|
||||
|
||||
/* spin_lock for APUPLL, since mdla0/1 shate apupll */
|
||||
if (domain == V_MDLA0 || domain == V_MDLA1) {
|
||||
spin_lock(&apupll_lock);
|
||||
}
|
||||
|
||||
switch (mode) {
|
||||
case CON0_PCW:
|
||||
pd = RG_PLL_SDM_PCW_CHG |
|
||||
(pd & POSDIV_MASK) << POSDIV_SHIFT | dds;
|
||||
apupwr_writel(pd, mixed_con1_addr[pll_idx]);
|
||||
udelay(PLL_READY_TIME_20US);
|
||||
break;
|
||||
case FHCTL_SW:
|
||||
/* pll con0 disable */
|
||||
_pll_en(pll_idx, false);
|
||||
apupwr_writel(dds, fhctl_dds_addr[pll_idx]);
|
||||
_set_postdiv_reg(pll_idx, pd);
|
||||
apupwr_setbits(PLL_TGL_ORG, fhctl_dds_addr[pll_idx]);
|
||||
udelay(PLL_CMD_READY_TIME_1US);
|
||||
/* pll con0 enable */
|
||||
_pll_en(pll_idx, true);
|
||||
udelay(PLL_READY_TIME_20US);
|
||||
break;
|
||||
case FHCTL_HW:
|
||||
old_pd = _pll_get_postdiv_reg(pll_idx);
|
||||
if (pd > old_pd) {
|
||||
_set_postdiv_reg(pll_idx, pd);
|
||||
apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]);
|
||||
} else {
|
||||
apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]);
|
||||
_set_postdiv_reg(pll_idx, pd);
|
||||
}
|
||||
ret = _fhctl_mon_done(pll_idx, dds);
|
||||
break;
|
||||
default:
|
||||
ERROR("%s input wrong mode: %d\n", __func__, mode);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* spin_lock for NPULL, since vpu0/1 share npupll */
|
||||
if (domain == V_VPU0 || domain == V_VPU1) {
|
||||
spin_unlock(&npupll_lock);
|
||||
}
|
||||
|
||||
/* spin_lock for APUPLL, since mdla0/1 share apupll */
|
||||
if (domain == V_MDLA0 || domain == V_MDLA1) {
|
||||
spin_unlock(&apupll_lock);
|
||||
}
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,341 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
|
||||
#include <apupwr_clkctl.h>
|
||||
#include <apupwr_clkctl_def.h>
|
||||
#include <mtk_plat_common.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
/* 8195 use PCW mode to change freq directly */
|
||||
enum pll_set_rate_mode PLL_MODE = CON0_PCW;
|
||||
|
||||
char *buck_domain_str[APUSYS_BUCK_DOMAIN_NUM] = {
|
||||
"V_VPU0",
|
||||
"V_VPU1",
|
||||
"V_MDLA0",
|
||||
"V_MDLA1",
|
||||
"V_APU_CONN",
|
||||
"V_TOP_IOMMU",
|
||||
"V_VCORE",
|
||||
};
|
||||
|
||||
uint32_t aacc_set[APUSYS_BUCK_DOMAIN_NUM] = {
|
||||
APU_ACC_CONFG_SET1, APU_ACC_CONFG_SET2,
|
||||
APU_ACC_CONFG_SET4, APU_ACC_CONFG_SET5,
|
||||
APU_ACC_CONFG_SET0, APU_ACC_CONFG_SET7
|
||||
};
|
||||
|
||||
uint32_t aacc_clr[APUSYS_BUCK_DOMAIN_NUM] = {
|
||||
APU_ACC_CONFG_CLR1, APU_ACC_CONFG_CLR2,
|
||||
APU_ACC_CONFG_CLR4, APU_ACC_CONFG_CLR5,
|
||||
APU_ACC_CONFG_CLR0, APU_ACC_CONFG_CLR7
|
||||
};
|
||||
|
||||
struct reg_seq {
|
||||
uint32_t address;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
static const struct reg_seq init_acc_cfg[] = {
|
||||
{ APU_ACC_CONFG_SET0, BIT(BIT_SEL_APU) },
|
||||
{ APU_ACC_CONFG_CLR0, BIT(BIT_CGEN_SOC) },
|
||||
{ APU_ACC_CONFG_SET0, BIT(BIT_SEL_APU_DIV2) },
|
||||
{ APU_ACC_CONFG_SET7, BIT(BIT_SEL_APU) },
|
||||
{ APU_ACC_CONFG_CLR7, BIT(BIT_CGEN_SOC) },
|
||||
{ APU_ACC_CONFG_SET7, BIT(BIT_SEL_APU_DIV2) },
|
||||
{ APU_ACC_CONFG_SET1, BIT(BIT_SEL_APU) },
|
||||
{ APU_ACC_CONFG_CLR1, BIT(BIT_CGEN_SOC) },
|
||||
{ APU_ACC_CONFG_SET1, BIT(BIT_SEL_APU_DIV2) },
|
||||
{ APU_ACC_CONFG_SET2, BIT(BIT_INVEN_OUT) },
|
||||
{ APU_ACC_CONFG_SET2, BIT(BIT_SEL_APU) },
|
||||
{ APU_ACC_CONFG_CLR2, BIT(BIT_CGEN_SOC) },
|
||||
{ APU_ACC_CONFG_SET2, BIT(BIT_SEL_APU_DIV2) },
|
||||
{ APU_ACC_CONFG_SET4, BIT(BIT_SEL_APU) },
|
||||
{ APU_ACC_CONFG_CLR4, BIT(BIT_CGEN_SOC) },
|
||||
{ APU_ACC_CONFG_SET4, BIT(BIT_SEL_APU_DIV2) },
|
||||
{ APU_ACC_CONFG_SET5, BIT(BIT_INVEN_OUT) },
|
||||
{ APU_ACC_CONFG_SET5, BIT(BIT_SEL_APU) },
|
||||
{ APU_ACC_CONFG_CLR5, BIT(BIT_CGEN_SOC) },
|
||||
{ APU_ACC_CONFG_SET5, BIT(BIT_SEL_APU_DIV2) },
|
||||
};
|
||||
|
||||
int32_t apupwr_smc_acc_init_all(void)
|
||||
{
|
||||
int32_t i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(init_acc_cfg); i++) {
|
||||
apupwr_writel(init_acc_cfg[i].val,
|
||||
init_acc_cfg[i].address);
|
||||
}
|
||||
|
||||
/* Deault ACC will raise APU_DIV_2 */
|
||||
apupwr_smc_pll_set_rate(BUCK_VCONN_DOMAIN_DEFAULT_FREQ,
|
||||
true, V_APU_CONN);
|
||||
|
||||
apupwr_smc_pll_set_rate(BUCK_VCONN_DOMAIN_DEFAULT_FREQ,
|
||||
true, V_TOP_IOMMU);
|
||||
|
||||
apupwr_smc_pll_set_rate(BUCK_VVPU_DOMAIN_DEFAULT_FREQ,
|
||||
true, V_VPU0);
|
||||
|
||||
apupwr_smc_pll_set_rate(BUCK_VMDLA_DOMAIN_DEFAULT_FREQ,
|
||||
true, V_MDLA0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void apupwr_smc_acc_top(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
apupwr_writel(BIT(BIT_CGEN_APU), aacc_set[V_APU_CONN]);
|
||||
apupwr_writel(BIT(BIT_CGEN_APU), aacc_set[V_TOP_IOMMU]);
|
||||
} else {
|
||||
apupwr_writel(BIT(BIT_CGEN_APU), aacc_clr[V_APU_CONN]);
|
||||
apupwr_writel(BIT(BIT_CGEN_APU), aacc_clr[V_TOP_IOMMU]);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* acc_clk_set_parent:ACC MUX select
|
||||
* 0. freq parameters here, only ACC clksrc is valid
|
||||
* 1. Switch between APUPLL <=> Parking (F26M, PARK)
|
||||
* 2. Turn on/off CG_F26M, CG_PARK, CG_SOC, but no CG_APU
|
||||
* 3. Clear APU Div2 while Parking
|
||||
* 4. Only use clksrc of APUPLL while ACC CG_APU is on
|
||||
*/
|
||||
int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain)
|
||||
{
|
||||
uint32_t acc_set = 0;
|
||||
uint32_t acc_clr = 0;
|
||||
int32_t ret = 0;
|
||||
|
||||
if (freq > DVFS_FREQ_ACC_APUPLL) {
|
||||
ERROR("%s wrong clksrc: %d\n", __func__, freq);
|
||||
ret = -EIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
switch (domain) {
|
||||
case V_VPU1:
|
||||
case V_VPU0:
|
||||
case V_MDLA1:
|
||||
case V_MDLA0:
|
||||
case V_APU_CONN:
|
||||
case V_TOP_IOMMU:
|
||||
acc_set = aacc_set[domain];
|
||||
acc_clr = aacc_clr[domain];
|
||||
break;
|
||||
default:
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Select park source */
|
||||
switch (freq) {
|
||||
case DVFS_FREQ_ACC_PARKING:
|
||||
/* Select park source */
|
||||
apupwr_writel(BIT(BIT_SEL_PARK), acc_set);
|
||||
apupwr_writel(BIT(BIT_SEL_F26M), acc_clr);
|
||||
/* Enable park cg */
|
||||
apupwr_writel(BIT(BIT_CGEN_PARK), acc_set);
|
||||
apupwr_writel(BIT(BIT_CGEN_F26M) | BIT(BIT_CGEN_SOC), acc_clr);
|
||||
/* Select park path */
|
||||
apupwr_writel(BIT(BIT_SEL_APU), acc_clr);
|
||||
/* clear apu div 2 */
|
||||
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr);
|
||||
break;
|
||||
|
||||
case DVFS_FREQ_ACC_APUPLL:
|
||||
/* Select park path */
|
||||
apupwr_writel(BIT(BIT_SEL_APU), acc_set);
|
||||
/* Clear park cg */
|
||||
apupwr_writel(BIT(BIT_CGEN_PARK) | BIT(BIT_CGEN_F26M) |
|
||||
BIT(BIT_CGEN_SOC), acc_clr);
|
||||
break;
|
||||
|
||||
case DVFS_FREQ_ACC_SOC:
|
||||
/* Select park source */
|
||||
apupwr_writel(BIT(BIT_SEL_PARK), acc_clr);
|
||||
apupwr_writel(BIT(BIT_SEL_F26M), acc_clr);
|
||||
/* Enable park cg */
|
||||
apupwr_writel(BIT(BIT_CGEN_SOC), acc_set);
|
||||
apupwr_writel(BIT(BIT_CGEN_F26M) | BIT(BIT_CGEN_PARK), acc_clr);
|
||||
/* Select park path */
|
||||
apupwr_writel(BIT(BIT_SEL_APU), acc_clr);
|
||||
/* clear apu div 2 */
|
||||
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr);
|
||||
break;
|
||||
|
||||
case DVFS_FREQ_ACC_26M:
|
||||
case DVFS_FREQ_NOT_SUPPORT:
|
||||
default:
|
||||
/* Select park source */
|
||||
apupwr_writel(BIT(BIT_SEL_F26M), acc_set);
|
||||
apupwr_writel(BIT(BIT_SEL_PARK), acc_clr);
|
||||
/* Enable park cg */
|
||||
apupwr_writel(BIT(BIT_CGEN_F26M), acc_set);
|
||||
apupwr_writel(BIT(BIT_CGEN_PARK) | BIT(BIT_CGEN_SOC), acc_clr);
|
||||
/* Select park path */
|
||||
apupwr_writel(BIT(BIT_SEL_APU), acc_clr);
|
||||
/* clear apu div 2 */
|
||||
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr);
|
||||
ERROR("[APUPWR] %s wrong ACC clksrc : %d, force assign 26M\n",
|
||||
__func__, freq);
|
||||
break;
|
||||
}
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
uint32_t acc_set0 = 0, acc_set1 = 0;
|
||||
|
||||
if (freq > DVFS_FREQ_MAX) {
|
||||
ERROR("%s wrong freq: %d\n", __func__, freq);
|
||||
ret = -EIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Switch to Parking src
|
||||
* 1. Need to switch out all ACCs sharing the same apupll
|
||||
*/
|
||||
switch (domain) {
|
||||
case V_MDLA0:
|
||||
case V_MDLA1:
|
||||
acc_set0 = APU_ACC_CONFG_SET4;
|
||||
acc_set1 = APU_ACC_CONFG_SET5;
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
|
||||
V_MDLA0);
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
|
||||
V_MDLA1);
|
||||
break;
|
||||
case V_VPU0:
|
||||
case V_VPU1:
|
||||
acc_set0 = APU_ACC_CONFG_SET1;
|
||||
acc_set1 = APU_ACC_CONFG_SET2;
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
|
||||
V_VPU0);
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
|
||||
V_VPU1);
|
||||
break;
|
||||
case V_APU_CONN:
|
||||
acc_set0 = APU_ACC_CONFG_SET0;
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
|
||||
V_APU_CONN);
|
||||
break;
|
||||
case V_TOP_IOMMU:
|
||||
acc_set0 = APU_ACC_CONFG_SET7;
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
|
||||
V_TOP_IOMMU);
|
||||
break;
|
||||
default:
|
||||
ERROR("[APUPWR] %s %d invalid domain (%d)\n",
|
||||
__func__, __LINE__, domain);
|
||||
ret = -EIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq);
|
||||
|
||||
if (div2) {
|
||||
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_set0);
|
||||
if (acc_set1) {
|
||||
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_set1);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Switch back to APUPLL
|
||||
* Only switch back to APUPLL while CG_APU on
|
||||
* And clksrc is not APUPLL
|
||||
*/
|
||||
switch (domain) {
|
||||
case V_VPU0:
|
||||
case V_VPU1:
|
||||
if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) &&
|
||||
!(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) {
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
|
||||
V_VPU0);
|
||||
}
|
||||
if ((apupwr_readl(acc_set1) & BIT(BIT_CGEN_APU)) &&
|
||||
!(apupwr_readl(acc_set1) & BIT(BIT_SEL_APU))) {
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
|
||||
V_VPU1);
|
||||
}
|
||||
break;
|
||||
case V_MDLA0:
|
||||
case V_MDLA1:
|
||||
if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) &&
|
||||
!(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) {
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
|
||||
V_MDLA0);
|
||||
}
|
||||
if ((apupwr_readl(acc_set1) & BIT(BIT_CGEN_APU)) &&
|
||||
!(apupwr_readl(acc_set1) & BIT(BIT_SEL_APU))) {
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
|
||||
V_MDLA1);
|
||||
}
|
||||
break;
|
||||
case V_APU_CONN:
|
||||
case V_TOP_IOMMU:
|
||||
if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) &&
|
||||
!(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) {
|
||||
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
|
||||
domain);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ERROR("[APUPWR] %s %d invalid domain (%d)\n",
|
||||
__func__, __LINE__, domain);
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
INFO("[%s][%d] set domain %d to freq %d\n",
|
||||
__func__, __LINE__, domain, (div2) ? (freq * 2) : freq);
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int32_t apupwr_smc_bulk_pll(bool enable)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
int32_t pll_idx;
|
||||
|
||||
if (enable) {
|
||||
for (pll_idx = APUPLL; pll_idx < APUPLL_MAX; pll_idx++) {
|
||||
ret = apu_pll_enable(pll_idx, enable, false);
|
||||
if (ret != 0) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (pll_idx = APUPLL2; pll_idx >= APUPLL; pll_idx--) {
|
||||
ret = apu_pll_enable(pll_idx, enable, false);
|
||||
if (ret != 0) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void apupwr_smc_bus_prot_cg_on(void)
|
||||
{
|
||||
apupwr_clrbits(AO_MD32_MNOC_MASK, APU_CSR_DUMMY_0);
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUPWR_CLKCTL_H
|
||||
#define APUPWR_CLKCTL_H
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <apupwr_clkctl_def.h>
|
||||
|
||||
int32_t apupwr_smc_acc_init_all(void);
|
||||
void apupwr_smc_acc_top(bool enable);
|
||||
int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
|
||||
int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);
|
||||
int32_t apupwr_smc_bulk_pll(bool enable);
|
||||
void apupwr_smc_bus_prot_cg_on(void);
|
||||
|
||||
int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en);
|
||||
int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
|
||||
enum pll_set_rate_mode mode, int32_t freq);
|
||||
#endif /* APUPWR_CLKCTL_H */
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef APUPWR_CLKCTL_DEF_H
|
||||
#define APUPWR_CLKCTL_DEF_H
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
enum dvfs_voltage_domain {
|
||||
V_VPU0 = 0,
|
||||
V_VPU1 = 1,
|
||||
V_MDLA0 = 2,
|
||||
V_MDLA1 = 3,
|
||||
V_APU_CONN = 4,
|
||||
V_TOP_IOMMU = 5,
|
||||
V_VCORE = 6,
|
||||
APUSYS_BUCK_DOMAIN_NUM = 7,
|
||||
};
|
||||
|
||||
enum dvfs_freq {
|
||||
DVFS_FREQ_NOT_SUPPORT = 0,
|
||||
DVFS_FREQ_ACC_26M = 1,
|
||||
DVFS_FREQ_ACC_PARKING = 2,
|
||||
DVFS_FREQ_ACC_SOC = 3,
|
||||
DVFS_FREQ_ACC_APUPLL = 4,
|
||||
DVFS_FREQ_00_026000_F = 26000,
|
||||
DVFS_FREQ_00_208000_F = 208000,
|
||||
DVFS_FREQ_00_238000_F = 238000,
|
||||
DVFS_FREQ_00_273000_F = 273000,
|
||||
DVFS_FREQ_00_312000_F = 312000,
|
||||
DVFS_FREQ_00_358000_F = 358000,
|
||||
DVFS_FREQ_00_385000_F = 385000,
|
||||
DVFS_FREQ_00_499200_F = 499200,
|
||||
DVFS_FREQ_00_500000_F = 500000,
|
||||
DVFS_FREQ_00_525000_F = 525000,
|
||||
DVFS_FREQ_00_546000_F = 546000,
|
||||
DVFS_FREQ_00_594000_F = 594000,
|
||||
DVFS_FREQ_00_624000_F = 624000,
|
||||
DVFS_FREQ_00_688000_F = 688000,
|
||||
DVFS_FREQ_00_687500_F = 687500,
|
||||
DVFS_FREQ_00_728000_F = 728000,
|
||||
DVFS_FREQ_00_800000_F = 800000,
|
||||
DVFS_FREQ_00_832000_F = 832000,
|
||||
DVFS_FREQ_00_960000_F = 960000,
|
||||
DVFS_FREQ_00_1100000_F = 1100000,
|
||||
};
|
||||
#define DVFS_FREQ_MAX (DVFS_FREQ_00_1100000_F)
|
||||
|
||||
enum pll_set_rate_mode {
|
||||
CON0_PCW = 0,
|
||||
FHCTL_SW = 1,
|
||||
FHCTL_HW = 2,
|
||||
PLL_SET_RATE_MODE_MAX = 3,
|
||||
};
|
||||
|
||||
enum apupll {
|
||||
APUPLL = 0,
|
||||
NPUPLL = 1,
|
||||
APUPLL1 = 2,
|
||||
APUPLL2 = 3,
|
||||
APUPLL_MAX = 4,
|
||||
};
|
||||
|
||||
#define BUCK_VVPU_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_273000_F)
|
||||
#define BUCK_VMDLA_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_312000_F)
|
||||
#define BUCK_VCONN_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_208000_F)
|
||||
|
||||
#define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
|
||||
#define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL)
|
||||
#define apupwr_readl(REG) mmio_read_32((uintptr_t)REG)
|
||||
#define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL)
|
||||
#define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL)
|
||||
#define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \
|
||||
mmio_clrsetbits_32((uintptr_t)REG, CLR_VAL, SET_VAL)
|
||||
|
||||
/* PLL and related register */
|
||||
#define APU_PLL_BASE (APUSYS_APU_PLL_BASE)
|
||||
#define APU_PLL4H_PLL1_CON0 (APU_PLL_BASE + 0x008)
|
||||
#define APU_PLL4H_PLL1_CON1 (APU_PLL_BASE + 0x00C)
|
||||
#define APU_PLL4H_PLL1_CON3 (APU_PLL_BASE + 0x014)
|
||||
|
||||
#define APU_PLL4H_PLL2_CON0 (APU_PLL_BASE + 0x018)
|
||||
#define APU_PLL4H_PLL2_CON1 (APU_PLL_BASE + 0x01C)
|
||||
#define APU_PLL4H_PLL2_CON3 (APU_PLL_BASE + 0x024)
|
||||
|
||||
#define APU_PLL4H_PLL3_CON0 (APU_PLL_BASE + 0x028)
|
||||
#define APU_PLL4H_PLL3_CON1 (APU_PLL_BASE + 0x02C)
|
||||
#define APU_PLL4H_PLL3_CON3 (APU_PLL_BASE + 0x034)
|
||||
|
||||
#define APU_PLL4H_PLL4_CON0 (APU_PLL_BASE + 0x038)
|
||||
#define APU_PLL4H_PLL4_CON1 (APU_PLL_BASE + 0x03C)
|
||||
#define APU_PLL4H_PLL4_CON3 (APU_PLL_BASE + 0x044)
|
||||
|
||||
#define APU_PLL4H_FHCTL_HP_EN (APU_PLL_BASE + 0x0E00)
|
||||
#define APU_PLL4H_FHCTL_UNITSLOPE_EN (APU_PLL_BASE + 0x0E04)
|
||||
#define APU_PLL4H_FHCTL_CLK_CON (APU_PLL_BASE + 0x0E08)
|
||||
#define APU_PLL4H_FHCTL_RST_CON (APU_PLL_BASE + 0x0E0C)
|
||||
#define APU_PLL4H_FHCTL_SLOPE0 (APU_PLL_BASE + 0x0E10)
|
||||
#define APU_PLL4H_FHCTL_SLOPE1 (APU_PLL_BASE + 0x0E14)
|
||||
#define APU_PLL4H_FHCTL_DSSC_CFG (APU_PLL_BASE + 0x0E18)
|
||||
#define APU_PLL4H_FHCTL_DSSC0_CON (APU_PLL_BASE + 0x0E1C)
|
||||
#define APU_PLL4H_FHCTL_DSSC1_CON (APU_PLL_BASE + 0x0E20)
|
||||
#define APU_PLL4H_FHCTL_DSSC2_CON (APU_PLL_BASE + 0x0E24)
|
||||
#define APU_PLL4H_FHCTL_DSSC3_CON (APU_PLL_BASE + 0x0E28)
|
||||
#define APU_PLL4H_FHCTL_DSSC4_CON (APU_PLL_BASE + 0x0E2C)
|
||||
#define APU_PLL4H_FHCTL_DSSC5_CON (APU_PLL_BASE + 0x0E30)
|
||||
#define APU_PLL4H_FHCTL_DSSC6_CON (APU_PLL_BASE + 0x0E34)
|
||||
#define APU_PLL4H_FHCTL_DSSC7_CON (APU_PLL_BASE + 0x0E38)
|
||||
#define APU_PLL4H_FHCTL0_CFG (APU_PLL_BASE + 0x0E3C)
|
||||
#define APU_PLL4H_FHCTL0_UPDNLMT (APU_PLL_BASE + 0x0E40)
|
||||
#define APU_PLL4H_FHCTL0_DDS (APU_PLL_BASE + 0x0E44)
|
||||
#define APU_PLL4H_FHCTL0_DVFS (APU_PLL_BASE + 0x0E48)
|
||||
#define APU_PLL4H_FHCTL0_MON (APU_PLL_BASE + 0x0E4C)
|
||||
#define APU_PLL4H_FHCTL1_CFG (APU_PLL_BASE + 0x0E50)
|
||||
#define APU_PLL4H_FHCTL1_UPDNLMT (APU_PLL_BASE + 0x0E54)
|
||||
#define APU_PLL4H_FHCTL1_DDS (APU_PLL_BASE + 0x0E58)
|
||||
#define APU_PLL4H_FHCTL1_DVFS (APU_PLL_BASE + 0x0E5C)
|
||||
#define APU_PLL4H_FHCTL1_MON (APU_PLL_BASE + 0x0E60)
|
||||
#define APU_PLL4H_FHCTL2_CFG (APU_PLL_BASE + 0x0E64)
|
||||
#define APU_PLL4H_FHCTL2_UPDNLMT (APU_PLL_BASE + 0x0E68)
|
||||
#define APU_PLL4H_FHCTL2_DDS (APU_PLL_BASE + 0x0E6C)
|
||||
#define APU_PLL4H_FHCTL2_DVFS (APU_PLL_BASE + 0x0E70)
|
||||
#define APU_PLL4H_FHCTL2_MON (APU_PLL_BASE + 0x0E74)
|
||||
#define APU_PLL4H_FHCTL3_CFG (APU_PLL_BASE + 0x0E78)
|
||||
#define APU_PLL4H_FHCTL3_UPDNLMT (APU_PLL_BASE + 0x0E7C)
|
||||
#define APU_PLL4H_FHCTL3_DDS (APU_PLL_BASE + 0x0E80)
|
||||
#define APU_PLL4H_FHCTL3_DVFS (APU_PLL_BASE + 0x0E84)
|
||||
#define APU_PLL4H_FHCTL3_MON (APU_PLL_BASE + 0x0E88)
|
||||
|
||||
/* PLL4H_PLLx_CON0 */
|
||||
#define RG_PLL_EN BIT(0)
|
||||
|
||||
/* PLL4H_PLLx_CON1 */
|
||||
#define RG_PLL_SDM_PCW_CHG BIT(31)
|
||||
#define POSDIV_SHIFT (24U)
|
||||
#define POSDIV_MASK (0x7)
|
||||
|
||||
/* PLL4H_PLLx_CON3 */
|
||||
#define DA_PLL_SDM_PWR_ON BIT(0)
|
||||
#define DA_PLL_SDM_ISO_EN BIT(1)
|
||||
|
||||
/* FHCTLx_DDS */
|
||||
#define DDS_MASK GENMASK_32(21, 0)
|
||||
#define PCW_FRACTIONAL_SHIFT 14U
|
||||
#define PLL_TGL_ORG BIT(31)
|
||||
|
||||
#define PLL_READY_TIME_20US (20U)
|
||||
#define PLL_CMD_READY_TIME_1US (1U)
|
||||
|
||||
#define FREQ_VCO_MIN (1500U) /* 1500MHz*/
|
||||
#define FREQ_FIN (26U) /* 26M*/
|
||||
|
||||
/* ACC and related register */
|
||||
#define APU_ACC_BASE (APUSYS_APU_ACC_BASE)
|
||||
#define APU_ACC_CONFG_SET0 (APU_ACC_BASE + 0x000)
|
||||
#define APU_ACC_CONFG_SET1 (APU_ACC_BASE + 0x004)
|
||||
#define APU_ACC_CONFG_SET2 (APU_ACC_BASE + 0x008)
|
||||
#define APU_ACC_CONFG_SET4 (APU_ACC_BASE + 0x010)
|
||||
#define APU_ACC_CONFG_SET5 (APU_ACC_BASE + 0x014)
|
||||
#define APU_ACC_CONFG_SET7 (APU_ACC_BASE + 0x01C)
|
||||
|
||||
#define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040)
|
||||
#define APU_ACC_CONFG_CLR1 (APU_ACC_BASE + 0x044)
|
||||
#define APU_ACC_CONFG_CLR2 (APU_ACC_BASE + 0x048)
|
||||
#define APU_ACC_CONFG_CLR4 (APU_ACC_BASE + 0x050)
|
||||
#define APU_ACC_CONFG_CLR5 (APU_ACC_BASE + 0x054)
|
||||
#define APU_ACC_CONFG_CLR7 (APU_ACC_BASE + 0x05C)
|
||||
|
||||
#define APU_ACC_FM_CONFG_SET (APU_ACC_BASE + 0x0C0)
|
||||
#define APU_ACC_FM_CONFG_CLR (APU_ACC_BASE + 0x0C4)
|
||||
#define APU_ACC_FM_SEL (APU_ACC_BASE + 0x0C8)
|
||||
#define APU_ACC_FM_CNT (APU_ACC_BASE + 0x0CC)
|
||||
|
||||
/* APU AO control */
|
||||
#define APU_AO_CTRL_BASE (APUSYS_APU_S_S_4_BASE)
|
||||
#define APU_CSR_DUMMY_0 (APU_AO_CTRL_BASE + 0x24)
|
||||
|
||||
#define AO_MD32_MNOC_MASK (BIT(1) | BIT(0))
|
||||
|
||||
#define BIT_CGEN_F26M (0)
|
||||
#define BIT_CGEN_PARK (1)
|
||||
#define BIT_CGEN_SOC (2)
|
||||
#define BIT_CGEN_APU (3)
|
||||
#define BIT_CGEN_OUT (4)
|
||||
#define BIT_SEL_PARK (8)
|
||||
#define BIT_SEL_F26M (9)
|
||||
#define BIT_SEL_APU_DIV2 (10)
|
||||
#define BIT_SEL_APU (11)
|
||||
#define BIT_SEL_PARK_SRC_OUT (12)
|
||||
#define BIT_INVEN_OUT (15)
|
||||
|
||||
#endif /* APUPWR_CLKCTL_DEF_H*/
|
||||
|
|
@ -8,6 +8,7 @@
|
|||
#include <drivers/console.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <apupwr_clkctl.h>
|
||||
#include <mtk_apusys.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
|
|
@ -61,6 +62,18 @@ int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
|
|||
mmio_read_32(AO_MD32_BOOT_CTRL),
|
||||
mmio_read_32(AO_MD32_SYS_CTRL));
|
||||
break;
|
||||
case MTK_SIP_APUPWR_BUS_PROT_CG_ON:
|
||||
apupwr_smc_bus_prot_cg_on();
|
||||
break;
|
||||
case MTK_SIP_APUPWR_BULK_PLL:
|
||||
ret = apupwr_smc_bulk_pll((bool)x2);
|
||||
break;
|
||||
case MTK_SIP_APUPWR_ACC_INIT_ALL:
|
||||
ret = apupwr_smc_acc_init_all();
|
||||
break;
|
||||
case MTK_SIP_APUPWR_ACC_TOP:
|
||||
apupwr_smc_acc_top((bool)x2);
|
||||
break;
|
||||
default:
|
||||
ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -10,8 +10,12 @@
|
|||
#include <stdint.h>
|
||||
|
||||
/* setup the SMC command ops */
|
||||
#define MTK_SIP_APU_START_MCU 0x00U
|
||||
#define MTK_SIP_APU_STOP_MCU 0x01U
|
||||
#define MTK_SIP_APU_START_MCU (0x00U)
|
||||
#define MTK_SIP_APU_STOP_MCU (0x01U)
|
||||
#define MTK_SIP_APUPWR_BUS_PROT_CG_ON (0x02U)
|
||||
#define MTK_SIP_APUPWR_BULK_PLL (0x03U)
|
||||
#define MTK_SIP_APUPWR_ACC_INIT_ALL (0x04U)
|
||||
#define MTK_SIP_APUPWR_ACC_TOP (0x05U)
|
||||
|
||||
/* AO Register */
|
||||
#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
|
||||
|
|
@ -20,28 +24,28 @@
|
|||
#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
|
||||
#define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14)
|
||||
|
||||
#define PRE_DEFINE_CACHE_TCM 0x3U
|
||||
#define PRE_DEFINE_CACHE 0x2U
|
||||
#define PRE_DEFINE_SHIFT_0G 0U
|
||||
#define PRE_DEFINE_SHIFT_1G 2U
|
||||
#define PRE_DEFINE_SHIFT_2G 4U
|
||||
#define PRE_DEFINE_SHIFT_3G 6U
|
||||
#define PRE_DEFINE_CACHE_TCM (0x3U)
|
||||
#define PRE_DEFINE_CACHE (0x2U)
|
||||
#define PRE_DEFINE_SHIFT_0G (0U)
|
||||
#define PRE_DEFINE_SHIFT_1G (2U)
|
||||
#define PRE_DEFINE_SHIFT_2G (4U)
|
||||
#define PRE_DEFINE_SHIFT_3G (6U)
|
||||
|
||||
#define SEC_FW_NON_SECURE 1U
|
||||
#define SEC_FW_SHIFT_NS 4U
|
||||
#define SEC_FW_DOMAIN_SHIFT 0U
|
||||
#define SEC_FW_NON_SECURE (1U)
|
||||
#define SEC_FW_SHIFT_NS (4U)
|
||||
#define SEC_FW_DOMAIN_SHIFT (0U)
|
||||
|
||||
#define SEC_USR_FW_NON_SECURE 1U
|
||||
#define SEC_USR_FW_SHIFT_NS 4U
|
||||
#define SEC_USR_FW_DOMAIN_SHIFT 0U
|
||||
#define SEC_USR_FW_NON_SECURE (1U)
|
||||
#define SEC_USR_FW_SHIFT_NS (4U)
|
||||
#define SEC_USR_FW_DOMAIN_SHIFT (0U)
|
||||
|
||||
#define SYS_CTRL_RUN 0U
|
||||
#define SYS_CTRL_STALL 1U
|
||||
#define SYS_CTRL_RUN (0U)
|
||||
#define SYS_CTRL_STALL (1U)
|
||||
|
||||
/* Reviser Register */
|
||||
#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100)
|
||||
#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104)
|
||||
|
||||
int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
|
||||
uint32_t *ret1);
|
||||
uint32_t *ret1);
|
||||
#endif /* MTK_APUSYS_H */
|
||||
|
|
|
|||
|
|
@ -60,7 +60,9 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT_SOC}/aarch64/platform_common.c \
|
||||
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
|
||||
${MTK_PLAT_SOC}/bl31_plat_setup.c \
|
||||
${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \
|
||||
${MTK_PLAT_SOC}/drivers/apusys/apupll.c \
|
||||
${MTK_PLAT_SOC}/drivers/apusys/apupwr_clkctl.c \
|
||||
${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \
|
||||
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
|
||||
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
|
||||
${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \
|
||||
|
|
|
|||
Loading…
Reference in New Issue