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feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call 

Add APU SiP call support for start/stop mcu.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e9568c0150436afa42
This commit is contained in:
Flora Fu 2021-11-01 16:43:47 +08:00
parent 339e4924a7
commit 88906b4437
5 changed files with 130 additions and 1 deletions
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70
plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c Normal file
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@ -0,0 +1,70 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/console.h>
#include <lib/mmio.h>
#include <mtk_apusys.h>
#include <plat/common/platform.h>
int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
uint32_t *ret1)
{
int32_t ret = 0L;
uint32_t request_ops;
request_ops = (uint32_t)x1;
switch (request_ops) {
case MTK_SIP_APU_START_MCU:
/* setup addr[33:32] in reviser */
mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
mmio_write_32(REVISER_USDRFW_CTXT, 0U);
/* setup secure sideband */
mmio_write_32(AO_SEC_FW,
(SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
(0U << SEC_FW_DOMAIN_SHIFT));
/* setup boot address */
mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
/* setup pre-define region */
mmio_write_32(AO_MD32_PRE_DEFINE,
(PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
/* release runstall */
mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
INFO("[APUSYS] rev(0x%08x,0x%08x)\n",
mmio_read_32(REVISER_SECUREFW_CTXT),
mmio_read_32(REVISER_USDRFW_CTXT));
INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n",
mmio_read_32(AO_SEC_FW),
mmio_read_32(AO_SEC_USR_FW),
mmio_read_32(AO_MD32_BOOT_CTRL),
mmio_read_32(AO_MD32_PRE_DEFINE),
mmio_read_32(AO_MD32_SYS_CTRL));
break;
case MTK_SIP_APU_STOP_MCU:
/* hold runstall */
mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
mmio_read_32(AO_MD32_BOOT_CTRL),
mmio_read_32(AO_MD32_SYS_CTRL));
break;
default:
ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
break;
}
return ret;
}

47
plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h Normal file
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@ -0,0 +1,47 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTK_APUSYS_H
#define MTK_APUSYS_H
#include <stdint.h>
/* setup the SMC command ops */
#define MTK_SIP_APU_START_MCU 0x00U
#define MTK_SIP_APU_STOP_MCU 0x01U
/* AO Register */
#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04)
#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08)
#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
#define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14)
#define PRE_DEFINE_CACHE_TCM 0x3U
#define PRE_DEFINE_CACHE 0x2U
#define PRE_DEFINE_SHIFT_0G 0U
#define PRE_DEFINE_SHIFT_1G 2U
#define PRE_DEFINE_SHIFT_2G 4U
#define PRE_DEFINE_SHIFT_3G 6U
#define SEC_FW_NON_SECURE 1U
#define SEC_FW_SHIFT_NS 4U
#define SEC_FW_DOMAIN_SHIFT 0U
#define SEC_USR_FW_NON_SECURE 1U
#define SEC_USR_FW_SHIFT_NS 4U
#define SEC_USR_FW_DOMAIN_SHIFT 0U
#define SYS_CTRL_RUN 0U
#define SYS_CTRL_STALL 1U
/* Reviser Register */
#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100)
#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104)
int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
uint32_t *ret1);
#endif /* MTK_APUSYS_H */

6
plat/mediatek/mt8195/include/plat_sip_calls.h
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@ -10,7 +10,7 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
#define MTK_PLAT_SIP_NUM_CALLS 4
#define MTK_PLAT_SIP_NUM_CALLS 6
/* DFD */
#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205
@ -20,4 +20,8 @@
#define MTK_SIP_DP_CONTROL_AARCH32 0x82000523
#define MTK_SIP_DP_CONTROL_AARCH64 0xC2000523
/* APUSYS SMC call */
#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E
#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E
#endif /* PLAT_SIP_CALLS_H */

6
plat/mediatek/mt8195/plat_sip_calls.c
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@ -9,6 +9,7 @@
#include <mt_dp.h>
#include <mt_spm.h>
#include <mt_spm_vcorefs.h>
#include <mtk_apusys.h>
#include <mtk_sip_svc.h>
#include <plat_dfd.h>
#include "plat_sip_calls.h"
@ -41,6 +42,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
ret = dfd_smc_dispatcher(x1, x2, x3, x4);
SMC_RET1(handle, ret);
break;
case MTK_SIP_APUSYS_CONTROL_AARCH32:
case MTK_SIP_APUSYS_CONTROL_AARCH64:
ret = apusys_kernel_ctrl(x1, x2, x3, x4, &ret_val);
SMC_RET2(handle, ret, ret_val);
break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;

2
plat/mediatek/mt8195/platform.mk
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@ -14,6 +14,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/timer/ \
-I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/drivers/apusys/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
-I${MTK_PLAT_SOC}/drivers/dfd \
-I${MTK_PLAT_SOC}/drivers/dp/ \
@ -59,6 +60,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \