Merge changes from topic "aa/sel2_support" into integration
* changes: S-EL2 Support: Check for AArch64 Add support for enabling S-EL2
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2bcc672f34
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@ -140,6 +140,8 @@
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#define ID_AA64PFR0_GIC_MASK ULL(0xf)
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#define ID_AA64PFR0_SVE_SHIFT U(32)
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#define ID_AA64PFR0_SVE_MASK ULL(0xf)
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#define ID_AA64PFR0_SEL2_SHIFT U(36)
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#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
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#define ID_AA64PFR0_MPAM_SHIFT U(40)
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#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
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#define ID_AA64PFR0_DIT_SHIFT U(48)
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@ -285,6 +287,7 @@
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#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
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#define SCR_ATA_BIT (U(1) << 26)
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#define SCR_FIEN_BIT (U(1) << 21)
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#define SCR_EEL2_BIT (U(1) << 18)
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#define SCR_API_BIT (U(1) << 17)
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#define SCR_APK_BIT (U(1) << 16)
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#define SCR_TWE_BIT (U(1) << 13)
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@ -181,6 +181,16 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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scr_el3 |= SCR_HCE_BIT;
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}
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/* Enable S-EL2 if the next EL is EL2 and security state is secure */
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if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
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if (GET_RW(ep->spsr) != MODE_RW_64) {
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ERROR("S-EL2 can not be used in AArch32.");
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panic();
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}
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scr_el3 |= SCR_EEL2_BIT;
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}
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/*
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* Initialise SCTLR_EL1 to the reset value corresponding to the target
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* execution state setting all fields rather than relying of the hw.
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