Merge "style(plat/arm/corstone1000): resolve checkpatch warnings" into integration
This commit is contained in:
commit
2d1ba79cde
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@ -57,8 +57,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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{
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.image_id = TOS_FW_CONFIG_ID,
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.image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
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.image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \
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CORSTONE1000_TOS_FW_CONFIG_BASE,
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.image_info.image_max_size = (CORSTONE1000_TOS_FW_CONFIG_LIMIT -
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CORSTONE1000_TOS_FW_CONFIG_BASE),
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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@ -36,10 +36,11 @@ static void set_fip_image_source(void)
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/*
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* metadata for firmware update is written at 0x0000 offset of the flash.
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* PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
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* As per firmware update spec, at a given point of time, only one bank is active.
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* This means, TF-A should boot from the same bank as TF-M.
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* As per firmware update spec, at a given point of time, only one bank
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* is active. This means, TF-A should boot from the same bank as TF-M.
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*/
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volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
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if (*boot_bank_flag > 1) {
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VERBOSE("Boot_bank is set higher than possible values");
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}
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@ -60,77 +60,45 @@
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/* SRAM (CVM) memory layout
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*
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* <ARM_TRUSTED_SRAM_BASE>
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*
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* partition size: sizeof(meminfo_t) = 16 bytes
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*
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* content: memory info area used by the next BL
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*
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* <ARM_FW_CONFIG_BASE>
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*
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* partition size: 4080 bytes
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*
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* <ARM_BL2_MEM_DESC_BASE>
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*
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* partition size: 4 KB
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*
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* content:
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*
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* Area where BL2 copies the images descriptors
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* content: Area where BL2 copies the images descriptors
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*
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* <ARM_BL_RAM_BASE> = <BL32_BASE>
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*
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* partition size: 688 KB
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*
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* content:
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*
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* BL32 (optee-os)
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* content: BL32 (optee-os)
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*
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* <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
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*
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* partition size: 8 KB
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*
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* content:
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*
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* BL32 config (TOS_FW_CONFIG)
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* content: BL32 config (TOS_FW_CONFIG)
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*
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* <BL31_BASE>
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*
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* partition size: 140 KB
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*
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* content:
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*
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* BL31
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* content: BL31
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*
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* <BL2_SIGNATURE_BASE>
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*
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* partition size: 4 KB
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*
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* content:
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*
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* MCUBOOT data needed to verify TF-A BL2
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* content: MCUBOOT data needed to verify TF-A BL2
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*
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* <BL2_BASE>
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*
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* partition size: 176 KB
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*
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* content:
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*
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* BL2
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* content: BL2
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*
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* <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
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*
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* partition size: 512 KB
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*
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* content:
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*
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* BL33 (u-boot)
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* content: BL33 (u-boot)
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*/
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/* DDR memory */
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#define ARM_DRAM1_BASE UL(0x80000000)
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#define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - 1)
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1)
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/* DRAM1 and DRAM2 are the same for corstone1000 */
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#define ARM_DRAM2_BASE ARM_DRAM1_BASE
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@ -139,8 +107,7 @@
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#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE +\
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ARM_NS_DRAM1_SIZE - 1)
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1)
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/* The first 8 KB of Trusted SRAM are used as shared memory */
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#define ARM_TRUSTED_SRAM_BASE UL(0x02000000)
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@ -150,8 +117,7 @@
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/* The remaining Trusted SRAM is used to load the BL images */
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#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */
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/* Last 512KB of CVM is allocated for shared RAM
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* as an example openAMP */
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/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
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#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K)
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#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \
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@ -162,23 +128,19 @@
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#define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */
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#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
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ARM_SHARED_RAM_SIZE)
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#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)
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#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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#define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */
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#define BL2_SIGNATURE_BASE (BL2_LIMIT - \
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PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_SIGNATURE_BASE (BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_BASE (BL2_LIMIT - \
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PLAT_ARM_MAX_BL2_SIZE + \
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BL2_SIGNATURE_SIZE)
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#define BL2_LIMIT (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE)
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#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#define BL31_BASE (BL2_SIGNATURE_BASE - \
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PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_BASE (BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_LIMIT BL2_SIGNATURE_BASE
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#define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \
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@ -187,11 +149,9 @@
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#define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE
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#define BL32_BASE ARM_BL_RAM_BASE
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#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - \
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BL32_BASE)
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#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE)
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#define BL32_LIMIT (BL32_BASE + \
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PLAT_ARM_MAX_BL32_SIZE)
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#define BL32_LIMIT (BL32_BASE + PLAT_ARM_MAX_BL32_SIZE)
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/* SPD_spmd settings */
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@ -237,10 +197,9 @@
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* FW_CONFIG is intended to host the device tree. Currently, This area is not
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* used because corstone1000 platform doesn't use a device tree at TF-A level.
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*/
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#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \
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+ sizeof(meminfo_t))
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#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \
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+ (ARM_SHARED_RAM_SIZE >> 1))
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#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t))
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#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \
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(ARM_SHARED_RAM_SIZE >> 1))
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/*
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* Boot parameters passed from BL2 to BL31/BL32 are stored here
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@ -255,8 +214,7 @@
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#define ARM_BL_REGIONS 3
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#define PLAT_ARM_MMAP_ENTRIES 8
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#define MAX_XLAT_TABLES 5
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#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
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ARM_BL_REGIONS)
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#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)
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#define MAX_IO_DEVICES 2
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#define MAX_IO_HANDLES 3
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#define MAX_IO_BLOCK_DEVICES 1
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@ -350,19 +308,17 @@
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#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL_CODE_END \
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- BL_CODE_BASE, \
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(BL_CODE_END - BL_CODE_BASE), \
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MT_CODE | MT_SECURE), \
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MAP_REGION_FLAT( \
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BL_RO_DATA_BASE, \
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BL_RO_DATA_END \
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- BL_RO_DATA_BASE, \
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(BL_RO_DATA_END - BL_RO_DATA_BASE), \
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MT_RO_DATA | MT_SECURE)
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#if USE_COHERENT_MEM
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#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
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BL_COHERENT_RAM_BASE, \
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BL_COHERENT_RAM_END \
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- BL_COHERENT_RAM_BASE, \
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(BL_COHERENT_RAM_END \
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- BL_COHERENT_RAM_BASE), \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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@ -372,8 +328,8 @@
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*/
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#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
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ARM_FW_CONFIG_BASE, \
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(ARM_FW_CONFIG_LIMIT- \
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ARM_FW_CONFIG_BASE), \
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(ARM_FW_CONFIG_LIMIT \
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- ARM_FW_CONFIG_BASE), \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define CORSTONE1000_DEVICE_BASE (0x1A000000)
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@ -426,10 +382,12 @@
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
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INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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