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Merge changes from topic "stm32mp_corrections_w40" into integration 

* changes:
  gpio: stm32_gpio: do not mix error code types
  fdts: stm32mp1: move FDCAN to PLL4_R
  mmc: increase delay between ACMD41 retries
  crypto: stm32_hash: align stm32_hash_update() prototype
This commit is contained in:
Soby Mathew 2019-10-03 13:32:45 +00:00 committed by TrustedFirmware Code Review
parent 34c4f86a62 243b61d15a
commit 2d35bc1386
6 changed files with 6 additions and 6 deletions
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2
drivers/mmc/mmc.c
View File

@ -361,7 +361,7 @@ static int sd_send_op_cond(void)
return 0;
}
mdelay(1);
mdelay(10);
}
ERROR("ACMD41 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);

2
drivers/st/gpio/stm32_gpio.c
View File

@ -165,7 +165,7 @@ int dt_set_pinctrl_config(int node)
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
return -FDT_ERR_NOTFOUND;
}
if (status == DT_DISABLED) {

2
fdts/stm32mp157a-avenger96.dts
View File

@ -246,7 +246,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q

2
fdts/stm32mp157a-dk1.dts
View File

@ -266,7 +266,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q

2
fdts/stm32mp157c-ed1.dts
View File

@ -272,7 +272,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q

2
include/drivers/st/stm32_hash.h
View File

@ -14,7 +14,7 @@ enum stm32_hash_algo_mode {
HASH_SHA256
};
int stm32_hash_update(const uint8_t *buffer, uint32_t length);
int stm32_hash_update(const uint8_t *buffer, size_t length);
int stm32_hash_final(uint8_t *digest);
int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length,
uint8_t *digest);