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Tegra132: set TZDRAM_BASE to 0xF5C00000 

The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2015-07-31 10:15:41 +05:30
parent 0bf1b022f2
commit 2ee2c4f0bb
2 changed files with 4 additions and 1 deletions
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3
docs/plat/nvidia-tegra.md
View File

@ -59,6 +59,9 @@ Preparing the BL31 image to run on Tegra SoCs
'CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> all'
Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>'
to the build command line.
Power Management
================
The PSCI implementation expects each platform to expose the 'power state'

2
plat/nvidia/tegra/soc/t132/platform_t132.mk
View File

@ -31,7 +31,7 @@
TEGRA_BOOT_UART_BASE := 0x70006300
$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
TZDRAM_BASE := 0xF1C00000
TZDRAM_BASE := 0xF5C00000
$(eval $(call add_define,TZDRAM_BASE))
PLATFORM_CLUSTER_COUNT := 1