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coverity: fix MISRA violations 

Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
  underscore, shall not be declared
- Type mismatch in BL1 SMC handlers and tspd_main.c

Change-Id: I7a92abf260da95acb0846b27c2997b59b059efc4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
This commit is contained in:
Zelalem 2020-02-12 10:37:03 -06:00
parent 572fcdd547
commit 2fe75a2de0
9 changed files with 41 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
bl1/bl1_fwu.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -55,11 +55,11 @@ static unsigned int sec_exec_image_id = INVALID_IMAGE_ID;
/******************************************************************************* /*******************************************************************************
* Top level handler for servicing FWU SMCs. * Top level handler for servicing FWU SMCs.
******************************************************************************/ ******************************************************************************/
register_t bl1_fwu_smc_handler(unsigned int smc_fid, u_register_t bl1_fwu_smc_handler(unsigned int smc_fid,
register_t x1, u_register_t x1,
register_t x2, u_register_t x2,
register_t x3, u_register_t x3,
register_t x4, u_register_t x4,
void *cookie, void *cookie,
void *handle, void *handle,
unsigned int flags) unsigned int flags)
@ -76,7 +76,7 @@ register_t bl1_fwu_smc_handler(unsigned int smc_fid,
SMC_RET1(handle, bl1_fwu_image_execute(x1, &handle, flags)); SMC_RET1(handle, bl1_fwu_image_execute(x1, &handle, flags));
case FWU_SMC_IMAGE_RESUME: case FWU_SMC_IMAGE_RESUME:
SMC_RET1(handle, bl1_fwu_image_resume(x1, &handle, flags)); SMC_RET1(handle, bl1_fwu_image_resume((register_t)x1, &handle, flags));
case FWU_SMC_SEC_IMAGE_DONE: case FWU_SMC_SEC_IMAGE_DONE:
SMC_RET1(handle, bl1_fwu_sec_image_done(&handle, flags)); SMC_RET1(handle, bl1_fwu_sec_image_done(&handle, flags));

14
bl1/bl1_main.c
View File

@ -226,11 +226,11 @@ void print_debug_loop_message(void)
/******************************************************************************* /*******************************************************************************
* Top level handler for servicing BL1 SMCs. * Top level handler for servicing BL1 SMCs.
******************************************************************************/ ******************************************************************************/
register_t bl1_smc_handler(unsigned int smc_fid, u_register_t bl1_smc_handler(unsigned int smc_fid,
register_t x1, u_register_t x1,
register_t x2, u_register_t x2,
register_t x3, u_register_t x3,
register_t x4, u_register_t x4,
void *cookie, void *cookie,
void *handle, void *handle,
unsigned int flags) unsigned int flags)
@ -269,12 +269,12 @@ register_t bl1_smc_handler(unsigned int smc_fid,
* BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
* compliance when invoking bl1_smc_handler. * compliance when invoking bl1_smc_handler.
******************************************************************************/ ******************************************************************************/
register_t bl1_smc_wrapper(uint32_t smc_fid, u_register_t bl1_smc_wrapper(uint32_t smc_fid,
void *cookie, void *cookie,
void *handle, void *handle,
unsigned int flags) unsigned int flags)
{ {
register_t x1, x2, x3, x4; u_register_t x1, x2, x3, x4;
assert(handle != NULL); assert(handle != NULL);

12
bl1/bl1_private.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -19,11 +19,11 @@ void bl1_arch_next_el_setup(void);
void bl1_prepare_next_image(unsigned int image_id); void bl1_prepare_next_image(unsigned int image_id);
register_t bl1_fwu_smc_handler(unsigned int smc_fid, u_register_t bl1_fwu_smc_handler(unsigned int smc_fid,
register_t x1, u_register_t x1,
register_t x2, u_register_t x2,
register_t x3, u_register_t x3,
register_t x4, u_register_t x4,
void *cookie, void *cookie,
void *handle, void *handle,
unsigned int flags); unsigned int flags);

4
drivers/cfi/v2m/v2m_flash.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -27,7 +27,7 @@
#define DWS_WORD_LOCK_RETRIES 1000 #define DWS_WORD_LOCK_RETRIES 1000
/* Helper macro to detect end of command */ /* Helper macro to detect end of command */
#define NOR_CMD_END (NOR_DWS | NOR_DWS << 16l) #define NOR_CMD_END (NOR_DWS | (NOR_DWS << 16l))
/* Helper macros to access two flash banks in parallel */ /* Helper macros to access two flash banks in parallel */
#define NOR_2X16(d) ((d << 16) | (d & 0xffff)) #define NOR_2X16(d) ((d << 16) | (d & 0xffff))

14
include/bl1/bl1.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -67,16 +67,16 @@
struct entry_point_info; struct entry_point_info;
register_t bl1_smc_wrapper(uint32_t smc_fid, u_register_t bl1_smc_wrapper(uint32_t smc_fid,
void *cookie, void *cookie,
void *handle, void *handle,
unsigned int flags); unsigned int flags);
register_t bl1_smc_handler(unsigned int smc_fid, u_register_t bl1_smc_handler(unsigned int smc_fid,
register_t x1, u_register_t x1,
register_t x2, u_register_t x2,
register_t x3, u_register_t x3,
register_t x4, u_register_t x4,
void *cookie, void *cookie,
void *handle, void *handle,
unsigned int flags); unsigned int flags);

8
include/lib/el3_runtime/aarch32/context.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -37,7 +37,7 @@
#define WORD_SHIFT U(2) #define WORD_SHIFT U(2)
#define DEFINE_REG_STRUCT(name, num_regs) \ #define DEFINE_REG_STRUCT(name, num_regs) \
typedef struct name { \ typedef struct name { \
uint32_t _regs[num_regs]; \ uint32_t ctx_regs[num_regs]; \
} __aligned(8) name##_t } __aligned(8) name##_t
/* Constants to determine the size of individual context structures */ /* Constants to determine the size of individual context structures */
@ -47,8 +47,8 @@ DEFINE_REG_STRUCT(regs, CTX_REG_ALL);
#undef CTX_REG_ALL #undef CTX_REG_ALL
#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> WORD_SHIFT]) #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[offset >> WORD_SHIFT])
#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> WORD_SHIFT]) \ #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[offset >> WORD_SHIFT]) \
= val) = val)
typedef struct cpu_context { typedef struct cpu_context {
regs_t regs_ctx; regs_t regs_ctx;

8
include/lib/el3_runtime/aarch64/context.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -230,7 +230,7 @@
#define DWORD_SHIFT U(3) #define DWORD_SHIFT U(3)
#define DEFINE_REG_STRUCT(name, num_regs) \ #define DEFINE_REG_STRUCT(name, num_regs) \
typedef struct name { \ typedef struct name { \
uint64_t _regs[num_regs]; \ uint64_t ctx_regs[num_regs]; \
} __aligned(16) name##_t } __aligned(16) name##_t
/* Constants to determine the size of individual context structures */ /* Constants to determine the size of individual context structures */
@ -288,8 +288,8 @@ DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL);
* Macros to access members of any of the above structures using their * Macros to access members of any of the above structures using their
* offsets * offsets
*/ */
#define read_ctx_reg(ctx, offset) ((ctx)->_regs[(offset) >> DWORD_SHIFT]) #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT])
#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[(offset) >> DWORD_SHIFT]) \ #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \
= (uint64_t) (val)) = (uint64_t) (val))
/* /*

4
lib/psci/psci_common.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -601,7 +601,7 @@ void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
unsigned int level; unsigned int level;
/* Unlock top down. No unlocking required for level 0. */ /* Unlock top down. No unlocking required for level 0. */
for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) { for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) {
parent_idx = parent_nodes[level - 1U]; parent_idx = parent_nodes[level - 1U];
psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
} }

4
services/spd/tspd/tspd_main.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -126,7 +126,7 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
* interrupt handling. * interrupt handling.
*/ */
if (get_yield_smc_active_flag(tsp_ctx->state)) { if (get_yield_smc_active_flag(tsp_ctx->state)) {
tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, tsp_ctx->saved_spsr_el3 = (uint32_t)SMC_GET_EL3(&tsp_ctx->cpu_ctx,
CTX_SPSR_EL3); CTX_SPSR_EL3);
tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx,
CTX_ELR_EL3); CTX_ELR_EL3);