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Merge changes from topic "stm32mp13" into integration 

* changes:
  feat(stm32mp1): select platform compilation either by flag or DT
  feat(stm32mp1-fdts): add support for STM32MP13 DK board
  feat(stm32mp1-fdts): add DDR support for STM32MP13
  feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
  feat(stm32mp1): updates for STM32MP13 device tree compilation
  feat(stm32mp1-fdts): add DT files for STM32MP13
  feat(dt-bindings): add TZC400 bindings for STM32MP13
  feat(stm32mp1): add "Boot mode" management for STM32MP13
  feat(stm32mp1): manage HSLV on STM32MP13
  feat(stm32mp1): add sdmmc compatible in platform define
  feat(st-sdmmc2): allow compatible to be defined in platform code
  feat(stm32mp1): update IO compensation on STM32MP13
  feat(stm32mp1): call pmic_voltages_init() in platform init
  feat(st-pmic): add pmic_voltages_init() function
  feat(stm32mp1): update CFG0 OTP for STM32MP13
  feat(stm32mp1): usb descriptor update for STM32MP13
  feat(st-clock): add clock driver for STM32MP13
  feat(dt-bindings): add bindings for STM32MP13
  feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
  feat(stm32mp1): use only one filter for TZC400 on STM32MP13
  feat(stm32mp1): add a second fixed regulator
  feat(stm32mp1): adaptations for STM32MP13 image header
  feat(stm32mp1): update boot API for header v2.0
  feat(stm32mp1): update IP addresses for STM32MP13
  feat(stm32mp1): add part numbers for STM32MP13
  feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
  feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
  feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
  feat(stm32mp1): remove unsupported features on STM32MP13
  feat(stm32mp1): update memory mapping for STM32MP13
  feat(stm32mp1): introduce new flag for STM32MP13
  feat(st): update stm32image tool for header v2
This commit is contained in:
Manish Pandey 2022-03-22 16:42:16 +01:00 committed by TrustedFirmware Code Review
parent 99d26d79c0 99a5d8d01d
commit 2ff6a49ea6
46 changed files with 12120 additions and 3058 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
docs/plat/stm32mp1.rst
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@ -2,15 +2,34 @@ STMicroelectronics STM32MP1
===========================
STM32MP1 is a microprocessor designed by STMicroelectronics
based on a dual Arm Cortex-A7.
based on Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
The STM32MP1 chip also embeds a Cortex-M4.
More information can be found on `STM32MP1 Series`_ page.
STM32MP1 Versions
-----------------
The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible:
There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
STM32MP13 Versions
~~~~~~~~~~~~~~~~~~
The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
- STM32MP131: Single Cortex-A7 core
- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
- STM32MP135: STM32MP133 + DCMIPP, LTDC
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
- A Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Cortex-A7 @ 900 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
STM32MP15 Versions
~~~~~~~~~~~~~~~~~~
The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
@ -131,6 +150,10 @@ Other configuration flags:
| Default: 115200
- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
| Default: 0
- | ``STM32MP13``: to select STM32MP13 variant configuration.
| Default: 0
- | ``STM32MP15``: to select STM32MP15 variant configuration.
| Default: 1
Boot with FIP

1097
drivers/st/clk/clk-stm32-core.c Normal file
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405
drivers/st/clk/clk-stm32-core.h Normal file
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@ -0,0 +1,405 @@
/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef CLK_STM32_CORE_H
#define CLK_STM32_CORE_H
struct mux_cfg {
uint16_t offset;
uint8_t shift;
uint8_t width;
uint8_t bitrdy;
};
struct gate_cfg {
uint16_t offset;
uint8_t bit_idx;
uint8_t set_clr;
};
struct clk_div_table {
unsigned int val;
unsigned int div;
};
struct div_cfg {
uint16_t offset;
uint8_t shift;
uint8_t width;
uint8_t flags;
uint8_t bitrdy;
const struct clk_div_table *table;
};
struct parent_cfg {
uint8_t num_parents;
const uint16_t *id_parents;
struct mux_cfg *mux;
};
struct stm32_clk_priv;
struct stm32_clk_ops {
unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate);
int (*get_parent)(struct stm32_clk_priv *priv, int id);
int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate,
unsigned long prate);
int (*enable)(struct stm32_clk_priv *priv, int id);
void (*disable)(struct stm32_clk_priv *priv, int id);
bool (*is_enabled)(struct stm32_clk_priv *priv, int id);
void (*init)(struct stm32_clk_priv *priv, int id);
};
struct clk_stm32 {
const char *name;
uint16_t binding;
uint16_t parent;
uint8_t flags;
void *clock_cfg;
const struct stm32_clk_ops *ops;
};
struct stm32_clk_priv {
uintptr_t base;
const uint32_t num;
const struct clk_stm32 *clks;
const struct parent_cfg *parents;
const uint32_t nb_parents;
const struct gate_cfg *gates;
const uint32_t nb_gates;
const struct div_cfg *div;
const uint32_t nb_div;
struct clk_oscillator_data *osci_data;
const uint32_t nb_osci_data;
uint32_t *gate_refcounts;
void *pdata;
};
struct stm32_clk_bypass {
uint16_t offset;
uint8_t bit_byp;
uint8_t bit_digbyp;
};
struct stm32_clk_css {
uint16_t offset;
uint8_t bit_css;
};
struct stm32_clk_drive {
uint16_t offset;
uint8_t drv_shift;
uint8_t drv_width;
uint8_t drv_default;
};
struct clk_oscillator_data {
const char *name;
uint16_t id_clk;
unsigned long frequency;
uint16_t gate_id;
uint16_t gate_rdy_id;
struct stm32_clk_bypass *bypass;
struct stm32_clk_css *css;
struct stm32_clk_drive *drive;
};
struct clk_fixed_rate {
const char *name;
unsigned long fixed_rate;
};
struct clk_gate_cfg {
uint32_t offset;
uint8_t bit_idx;
};
/* CLOCK FLAGS */
#define CLK_IS_CRITICAL BIT(0)
#define CLK_IGNORE_UNUSED BIT(1)
#define CLK_SET_RATE_PARENT BIT(2)
#define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
#define MUX_MAX_PARENTS U(0x8000)
#define MUX_PARENT_MASK GENMASK(14, 0)
#define MUX_FLAG U(0x8000)
#define MUX(mux) ((mux) | MUX_FLAG)
#define NO_GATE 0
#define _NO_ID UINT16_MAX
#define CLK_IS_ROOT UINT16_MAX
#define MUX_NO_BIT_RDY UINT8_MAX
#define DIV_NO_BIT_RDY UINT8_MAX
#define MASK_WIDTH_SHIFT(_width, _shift) \
GENMASK(((_width) + (_shift) - 1U), (_shift))
int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base);
void clk_stm32_enable_critical_clocks(void);
struct stm32_clk_priv *clk_stm32_get_priv(void);
int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id);
const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id);
void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass);
void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv);
void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css);
int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, bool ready_on);
int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on);
int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id);
int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id);
const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id);
const char *clk_stm32_get_name(struct stm32_clk_priv *priv, unsigned long binding_id);
int clk_stm32_get_counter(unsigned long binding_id);
void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id);
int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id);
int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int id, int src_id);
int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel);
int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int id);
int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx);
int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id);
unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id);
unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id);
bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag);
int _clk_stm32_enable(struct stm32_clk_priv *priv, int id);
void _clk_stm32_disable(struct stm32_clk_priv *priv, int id);
int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id);
void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id);
bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id);
int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id,
unsigned long rate, unsigned long parent_rate);
int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
unsigned long prate);
unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv,
int div_id,
unsigned long prate);
unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx,
unsigned long prate);
int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx);
void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx);
bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id);
bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx);
uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id);
int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value);
int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel);
int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id);
int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb);
#ifdef CFG_STM32_CLK_DEBUG
void clk_stm32_display_clock_info(void);
#endif
struct clk_stm32_div_cfg {
int id;
};
#define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_binding),\
.parent = (_parent),\
.flags = (_flags),\
.clock_cfg = &(struct clk_stm32_div_cfg){\
.id = (_div_id),\
},\
.ops = &clk_stm32_divider_ops,\
}
struct clk_stm32_gate_cfg {
int id;
};
#define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_binding),\
.parent = (_parent),\
.flags = (_flags),\
.clock_cfg = &(struct clk_stm32_gate_cfg){\
.id = (_gate_id),\
},\
.ops = &clk_stm32_gate_ops,\
}
struct fixed_factor_cfg {
unsigned int mult;
unsigned int div;
};
unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
int _idx, unsigned long prate);
#define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_idx),\
.parent = (_parent),\
.clock_cfg = &(struct fixed_factor_cfg){\
.mult = (_mult),\
.div = (_div),\
},\
.ops = &clk_fixed_factor_ops,\
}
#define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_binding),\
.parent = (_parent),\
.flags = (_flags),\
.clock_cfg = &(struct clk_gate_cfg){\
.offset = (_offset),\
.bit_idx = (_bit_idx),\
},\
.ops = &clk_gate_ops,\
}
#define STM32_MUX(idx, _binding, _mux_id, _flags) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_binding),\
.parent = (MUX(_mux_id)),\
.flags = (_flags),\
.clock_cfg = NULL,\
.ops = (&clk_mux_ops),\
}
struct clk_timer_cfg {
uint32_t apbdiv;
uint32_t timpre;
};
#define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_idx),\
.parent = (_parent),\
.flags = (CLK_SET_RATE_PARENT | (_flags)),\
.clock_cfg = &(struct clk_timer_cfg){\
.apbdiv = (_apbdiv),\
.timpre = (_timpre),\
},\
.ops = &clk_timer_ops,\
}
struct clk_stm32_fixed_rate_cfg {
unsigned long rate;
};
#define CLK_FIXED_RATE(idx, _binding, _rate) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_binding),\
.parent = (CLK_IS_ROOT),\
.clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\
.rate = (_rate),\
},\
.ops = &clk_stm32_fixed_rate_ops,\
}
#define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\
.offset = (_offset),\
.bit_byp = (_bit_byp),\
.bit_digbyp = (_bit_digbyp),\
}
#define CSS(_offset, _bit_css) &(struct stm32_clk_css){\
.offset = (_offset),\
.bit_css = (_bit_css),\
}
#define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\
.offset = (_offset),\
.drv_shift = (_shift),\
.drv_width = (_width),\
.drv_default = (_default),\
}
#define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \
[(idx_osc)] = (struct clk_oscillator_data){\
.name = (_name),\
.id_clk = (_id),\
.gate_id = (_gate_id),\
.gate_rdy_id = (_gate_rdy_id),\
.bypass = (_bypass),\
.css = (_css),\
.drive = (_drive),\
}
struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id);
void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id);
bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id);
int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id);
void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id);
struct stm32_osc_cfg {
int osc_id;
};
#define CLK_OSC(idx, _idx, _parent, _osc_id) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_idx),\
.parent = (_parent),\
.flags = CLK_IS_CRITICAL,\
.clock_cfg = &(struct stm32_osc_cfg){\
.osc_id = (_osc_id),\
},\
.ops = &clk_stm32_osc_ops,\
}
#define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \
[(idx)] = (struct clk_stm32){ \
.name = #idx,\
.binding = (_idx),\
.parent = (_parent),\
.flags = CLK_IS_CRITICAL,\
.clock_cfg = &(struct stm32_osc_cfg){\
.osc_id = (_osc_id),\
},\
.ops = &clk_stm32_osc_nogate_ops,\
}
extern const struct stm32_clk_ops clk_mux_ops;
extern const struct stm32_clk_ops clk_stm32_divider_ops;
extern const struct stm32_clk_ops clk_stm32_gate_ops;
extern const struct stm32_clk_ops clk_fixed_factor_ops;
extern const struct stm32_clk_ops clk_gate_ops;
extern const struct stm32_clk_ops clk_timer_ops;
extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops;
extern const struct stm32_clk_ops clk_stm32_osc_ops;
extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops;
#endif /* CLK_STM32_CORE_H */

2334
drivers/st/clk/clk-stm32mp13.c Normal file
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2
drivers/st/mmc/stm32_sdmmc2.c
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@ -125,7 +125,9 @@
#define POWER_OFF_DELAY 2
#define POWER_ON_DELAY 1
#ifndef DT_SDMMC2_COMPAT
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
#endif
static void stm32_sdmmc2_init(void);
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);

43
drivers/st/pmic/stm32mp_pmic.c
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@ -219,17 +219,20 @@ int pmic_ddr_power_init(enum ddr_type ddr_type)
{
int status;
uint16_t buck3_min_mv;
struct rdev *buck2, *buck3, *ldo3, *vref;
struct rdev *buck2, *buck3, *vref;
struct rdev *ldo3 __unused;
buck2 = regulator_get_by_name("buck2");
if (buck2 == NULL) {
return -ENOENT;
}
#if STM32MP15
ldo3 = regulator_get_by_name("ldo3");
if (ldo3 == NULL) {
return -ENOENT;
}
#endif
vref = regulator_get_by_name("vref_ddr");
if (vref == NULL) {
@ -238,10 +241,12 @@ int pmic_ddr_power_init(enum ddr_type ddr_type)
switch (ddr_type) {
case STM32MP_DDR3:
#if STM32MP15
status = regulator_set_flag(ldo3, REGUL_SINK_SOURCE);
if (status != 0) {
return status;
}
#endif
status = regulator_set_min_voltage(buck2);
if (status != 0) {
@ -258,10 +263,12 @@ int pmic_ddr_power_init(enum ddr_type ddr_type)
return status;
}
#if STM32MP15
status = regulator_enable(ldo3);
if (status != 0) {
return status;
}
#endif
break;
case STM32MP_LPDDR2:
@ -278,6 +285,7 @@ int pmic_ddr_power_init(enum ddr_type ddr_type)
regulator_get_range(buck3, &buck3_min_mv, NULL);
#if STM32MP15
if (buck3_min_mv != 1800) {
status = regulator_set_min_voltage(ldo3);
if (status != 0) {
@ -289,16 +297,19 @@ int pmic_ddr_power_init(enum ddr_type ddr_type)
return status;
}
}
#endif
status = regulator_set_min_voltage(buck2);
if (status != 0) {
return status;
}
#if STM32MP15
status = regulator_enable(ldo3);
if (status != 0) {
return status;
}
#endif
status = regulator_enable(buck2);
if (status != 0) {
@ -318,6 +329,36 @@ int pmic_ddr_power_init(enum ddr_type ddr_type)
return 0;
}
int pmic_voltages_init(void)
{
#if STM32MP13
struct rdev *buck1, *buck4;
int status;
buck1 = regulator_get_by_name("buck1");
if (buck1 == NULL) {
return -ENOENT;
}
buck4 = regulator_get_by_name("buck4");
if (buck4 == NULL) {
return -ENOENT;
}
status = regulator_set_min_voltage(buck1);
if (status != 0) {
return status;
}
status = regulator_set_min_voltage(buck4);
if (status != 0) {
return status;
}
#endif
return 0;
}
enum {
STPMIC1_BUCK1 = 0,
STPMIC1_BUCK2,

130
fdts/stm32mp13-bl2.dtsi Normal file
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@ -0,0 +1,130 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
*/
/ {
aliases {
#if !STM32MP_EMMC && !STM32MP_SDMMC
/delete-property/ mmc0;
/delete-property/ mmc1;
#endif
/delete-property/ ethernet0;
/delete-property/ ethernet1;
};
cpus {
cpu@0 {
/delete-property/ operating-points-v2;
};
};
/delete-node/ cpu0-opp-table;
/delete-node/ psci;
soc {
/delete-node/ sram@30000000;
/delete-node/ timer@40000000;
/delete-node/ timer@40001000;
/delete-node/ timer@40002000;
/delete-node/ timer@40003000;
/delete-node/ timer@40004000;
/delete-node/ timer@40005000;
/delete-node/ timer@40009000;
/delete-node/ spi@4000b000;
/delete-node/ audio-controller@4000b000;
/delete-node/ spi@4000c000;
/delete-node/ audio-controller@4000c000;
/delete-node/ audio-controller@4000d000;
/delete-node/ i2c@40012000;
/delete-node/ i2c@40013000;
/delete-node/ timer@44000000;
/delete-node/ timer@44001000;
/delete-node/ spi@44004000;
/delete-node/ audio-controller@44004000;
/delete-node/ sai@4400a000;
/delete-node/ sai@4400b000;
/delete-node/ dfsdm@4400d000;
/delete-node/ can@4400e000;
/delete-node/ can@4400f000;
/delete-node/ dma-controller@48000000;
/delete-node/ dma-controller@48001000;
/delete-node/ dma-router@48002000;
/delete-node/ adc@48003000;
/delete-node/ adc@48004000;
/delete-node/ dma@48005000;
/delete-node/ dma-router@48006000;
#if !STM32MP_USB_PROGRAMMER
/delete-node/ usb-otg@49000000;
#endif
/delete-node/ spi@4c002000;
/delete-node/ spi@4c003000;
/delete-node/ timer@4c007000;
/delete-node/ timer@4c008000;
/delete-node/ timer@4c009000;
/delete-node/ timer@4c00a000;
/delete-node/ timer@4c00b000;
/delete-node/ timer@4c00c000;
/delete-node/ timer@50021000;
/delete-node/ timer@50022000;
/delete-node/ timer@50023000;
/delete-node/ timer@50024000;
/delete-node/ vrefbuf@50025000;
/delete-node/ thermal@50028000;
/delete-node/ hdp@5002a000;
/delete-node/ dma-controller@58000000;
#if !STM32MP_RAW_NAND
/delete-node/ memory-controller@58002000;
#endif
#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR
/delete-node/ spi@58003000;
#endif
#if !STM32MP_EMMC && !STM32MP_SDMMC
/delete-node/ mmc@58005000;
/delete-node/ mmc@58007000;
#endif
/delete-node/ crc@58009000;
/delete-node/ stmmac-axi-config;
/delete-node/ eth1@5800a000;
#if !STM32MP_USB_PROGRAMMER
/delete-node/ usbh-ohci@5800c000;
/delete-node/ usbh-ehci@5800d000;
#endif
/delete-node/ eth2@5800e000;
/delete-node/ dcmipp@5a000000;
/delete-node/ display-controller@5a001000;
#if !STM32MP_USB_PROGRAMMER
/delete-node/ usbphyc@5a006000;
#endif
/delete-node/ perf@5a007000;
/delete-node/ rtc@5c004000;
/delete-node/ tamp@5c00a000;
/delete-node/ stgen@5c008000;
pin-controller@50002000 {
#if !STM32MP_EMMC && !STM32MP_SDMMC
/delete-node/ sdmmc1-b4-0;
/delete-node/ sdmmc2-b4-0;
#endif
};
};
/*
* UUID's here are UUID RFC 4122 compliant meaning fieds are stored in
* network order (big endian)
*/
st-io_policies {
fip-handles {
compatible = "st,io-fip-handle";
fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e";
bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288";
bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
};
};
};

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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*/
&ddr {
st,mem-name = DDR_MEM_NAME;
st,mem-speed = <DDR_MEM_SPEED>;
st,mem-size = <DDR_MEM_SIZE>;
st,ctl-reg = <
DDR_MSTR
DDR_MRCTRL0
DDR_MRCTRL1
DDR_DERATEEN
DDR_DERATEINT
DDR_PWRCTL
DDR_PWRTMG
DDR_HWLPCTL
DDR_RFSHCTL0
DDR_RFSHCTL3
DDR_CRCPARCTL0
DDR_ZQCTL0
DDR_DFITMG0
DDR_DFITMG1
DDR_DFILPCFG0
DDR_DFIUPD0
DDR_DFIUPD1
DDR_DFIUPD2
DDR_DFIPHYMSTR
DDR_ODTMAP
DDR_DBG0
DDR_DBG1
DDR_DBGCMD
DDR_POISONCFG
DDR_PCCFG
>;
st,ctl-timing = <
DDR_RFSHTMG
DDR_DRAMTMG0
DDR_DRAMTMG1
DDR_DRAMTMG2
DDR_DRAMTMG3
DDR_DRAMTMG4
DDR_DRAMTMG5
DDR_DRAMTMG6
DDR_DRAMTMG7
DDR_DRAMTMG8
DDR_DRAMTMG14
DDR_ODTCFG
>;
st,ctl-map = <
DDR_ADDRMAP1
DDR_ADDRMAP2
DDR_ADDRMAP3
DDR_ADDRMAP4
DDR_ADDRMAP5
DDR_ADDRMAP6
DDR_ADDRMAP9
DDR_ADDRMAP10
DDR_ADDRMAP11
>;
st,ctl-perf = <
DDR_SCHED
DDR_SCHED1
DDR_PERFHPR1
DDR_PERFLPR1
DDR_PERFWR1
DDR_PCFGR_0
DDR_PCFGW_0
DDR_PCFGQOS0_0
DDR_PCFGQOS1_0
DDR_PCFGWQOS0_0
DDR_PCFGWQOS1_0
>;
st,phy-reg = <
DDR_PGCR
DDR_ACIOCR
DDR_DXCCR
DDR_DSGCR
DDR_DCR
DDR_ODTCR
DDR_ZQ0CR1
DDR_DX0GCR
DDR_DX1GCR
>;
st,phy-timing = <
DDR_PTR0
DDR_PTR1
DDR_PTR2
DDR_DTPR0
DDR_DTPR1
DDR_DTPR2
DDR_MR0
DDR_MR1
DDR_MR2
DDR_MR3
>;
};
#undef DDR_MEM_NAME
#undef DDR_MEM_SPEED
#undef DDR_MEM_SIZE
#undef DDR_MSTR
#undef DDR_MRCTRL0
#undef DDR_MRCTRL1
#undef DDR_DERATEEN
#undef DDR_DERATEINT
#undef DDR_PWRCTL
#undef DDR_PWRTMG
#undef DDR_HWLPCTL
#undef DDR_RFSHCTL0
#undef DDR_RFSHCTL3
#undef DDR_RFSHTMG
#undef DDR_CRCPARCTL0
#undef DDR_DRAMTMG0
#undef DDR_DRAMTMG1
#undef DDR_DRAMTMG2
#undef DDR_DRAMTMG3
#undef DDR_DRAMTMG4
#undef DDR_DRAMTMG5
#undef DDR_DRAMTMG6
#undef DDR_DRAMTMG7
#undef DDR_DRAMTMG8
#undef DDR_DRAMTMG14
#undef DDR_ZQCTL0
#undef DDR_DFITMG0
#undef DDR_DFITMG1
#undef DDR_DFILPCFG0
#undef DDR_DFIUPD0
#undef DDR_DFIUPD1
#undef DDR_DFIUPD2
#undef DDR_DFIPHYMSTR
#undef DDR_ADDRMAP1
#undef DDR_ADDRMAP2
#undef DDR_ADDRMAP3
#undef DDR_ADDRMAP4
#undef DDR_ADDRMAP5
#undef DDR_ADDRMAP6
#undef DDR_ADDRMAP9
#undef DDR_ADDRMAP10
#undef DDR_ADDRMAP11
#undef DDR_ODTCFG
#undef DDR_ODTMAP
#undef DDR_SCHED
#undef DDR_SCHED1
#undef DDR_PERFHPR1
#undef DDR_PERFLPR1
#undef DDR_PERFWR1
#undef DDR_DBG0
#undef DDR_DBG1
#undef DDR_DBGCMD
#undef DDR_POISONCFG
#undef DDR_PCCFG
#undef DDR_PCFGR_0
#undef DDR_PCFGW_0
#undef DDR_PCFGQOS0_0
#undef DDR_PCFGQOS1_0
#undef DDR_PCFGWQOS0_0
#undef DDR_PCFGWQOS1_0
#undef DDR_PGCR
#undef DDR_PTR0
#undef DDR_PTR1
#undef DDR_PTR2
#undef DDR_ACIOCR
#undef DDR_DXCCR
#undef DDR_DSGCR
#undef DDR_DCR
#undef DDR_DTPR0
#undef DDR_DTPR1
#undef DDR_DTPR2
#undef DDR_MR0
#undef DDR_MR1
#undef DDR_MR2
#undef DDR_MR3
#undef DDR_ODTCR
#undef DDR_ZQ0CR1
#undef DDR_DX0GCR
#undef DDR_DX1GCR

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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*
* STM32MP135C DISCO BOARD configuration
* 1x DDR3L 4Gb, 16-bit, 533MHz.
* Reference used MT41K256M16TW-107 P from Micron
*
* DDR type / Platform DDR3/3L
* freq 533MHz
* width 16
* datasheet 1
* DDR density 4
* timing mode optimized
* Scheduling/QoS options : type = 6
* address mapping : RBC
* Tc > + 85C : N
*/
#define DDR_MEM_NAME "DDR3-1066 bin F 1x4Gb 533MHz v1.53"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00040401
#define DDR_MRCTRL0 0x00000010
#define DDR_MRCTRL1 0x00000000
#define DDR_DERATEEN 0x00000000
#define DDR_DERATEINT 0x00800000
#define DDR_PWRCTL 0x00000000
#define DDR_PWRTMG 0x00400010
#define DDR_HWLPCTL 0x00000000
#define DDR_RFSHCTL0 0x00210000
#define DDR_RFSHCTL3 0x00000000
#define DDR_RFSHTMG 0x0081008B
#define DDR_CRCPARCTL0 0x00000000
#define DDR_DRAMTMG0 0x121B2414
#define DDR_DRAMTMG1 0x000A041B
#define DDR_DRAMTMG2 0x0607080F
#define DDR_DRAMTMG3 0x0050400C
#define DDR_DRAMTMG4 0x07040607
#define DDR_DRAMTMG5 0x06060403
#define DDR_DRAMTMG6 0x02020002
#define DDR_DRAMTMG7 0x00000202
#define DDR_DRAMTMG8 0x00001005
#define DDR_DRAMTMG14 0x000000A0
#define DDR_ZQCTL0 0xC2000040
#define DDR_DFITMG0 0x02050105
#define DDR_DFITMG1 0x00000202
#define DDR_DFILPCFG0 0x07000000
#define DDR_DFIUPD0 0xC0400003
#define DDR_DFIUPD1 0x00000000
#define DDR_DFIUPD2 0x00000000
#define DDR_DFIPHYMSTR 0x00000000
#define DDR_ADDRMAP1 0x00080808
#define DDR_ADDRMAP2 0x00000000
#define DDR_ADDRMAP3 0x00000000
#define DDR_ADDRMAP4 0x00001F1F
#define DDR_ADDRMAP5 0x07070707
#define DDR_ADDRMAP6 0x0F070707
#define DDR_ADDRMAP9 0x00000000
#define DDR_ADDRMAP10 0x00000000
#define DDR_ADDRMAP11 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
#define DDR_SCHED 0x00000F01
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x00000001
#define DDR_PERFLPR1 0x04000200
#define DDR_PERFWR1 0x08000400
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00000000
#define DDR_PCFGW_0 0x00000000
#define DDR_PCFGQOS0_0 0x00100009
#define DDR_PCFGQOS1_0 0x00000020
#define DDR_PCFGWQOS0_0 0x01100B03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
#define DDR_PTR1 0x04841104
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x36D477D0
#define DDR_DTPR1 0x098B00D8
#define DDR_DTPR2 0x10023600
#define DDR_MR0 0x00000830
#define DDR_MR1 0x00000000
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX1GCR 0x0000CE81
#include "stm32mp13-ddr.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*/
#include <common/tbbr/tbbr_img_def.h>
#include <dt-bindings/soc/stm32mp13-tzc400.h>
#include <platform_def.h>
#ifndef DDR_SIZE
#error "DDR_SIZE is not defined"
#endif
#define DDR_NS_BASE STM32MP_DDR_BASE
#define DDR_SEC_SIZE 0x01e00000
#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE))
#define DDR_SHARE_SIZE 0x00200000
#define DDR_SHARE_BASE (DDR_SEC_BASE - DDR_SHARE_SIZE)
#define DDR_NS_SIZE (DDR_SHARE_BASE - DDR_NS_BASE)
/dts-v1/;
/ {
dtb-registry {
compatible = "fconf,dyn_cfg-dtb_registry";
hw-config {
load-address = <0x0 STM32MP_HW_CONFIG_BASE>;
max-size = <STM32MP_HW_CONFIG_MAX_SIZE>;
id = <HW_CONFIG_ID>;
};
nt_fw {
load-address = <0x0 STM32MP_BL33_BASE>;
max-size = <STM32MP_BL33_MAX_SIZE>;
id = <BL33_IMAGE_ID>;
};
tos_fw {
load-address = <0x0 DDR_SEC_BASE>;
max-size = <DDR_SEC_SIZE>;
id = <BL32_IMAGE_ID>;
};
};
st-mem-firewall {
compatible = "st,mem-firewall";
memory-ranges = <
DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR
DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)
DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('B', 9, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <2>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
slew-rate = <2>;
drive-push-pull;
bias-pull-up;
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
bias-pull-up;
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
bias-pull-up;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clocks = <&rcc CK_MPU>;
clock-names = "cpu";
nvmem-cells = <&part_number_otp>;
nvmem-cell-names = "part_number";
};
};
nvmem_layout: nvmem_layout@0 {
compatible = "st,stm32-nvmem-layout";
nvmem-cells = <&cfg0_otp>,
<&part_number_otp>,
<&monotonic_otp>,
<&nand_otp>,
<&nand2_otp>,
<&uid_otp>,
<&hw2_otp>;
nvmem-cell-names = "cfg0_otp",
"part_number_otp",
"monotonic_otp",
"nand_otp",
"nand2_otp",
"uid_otp",
"hw2_otp";
};
clocks {
clk_csi: clk-csi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
};
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
};
intc: interrupt-controller@a0021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xa0021000 0x1000>,
<0xa0022000 0x2000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
usart3: serial@4000f000 {
compatible = "st,stm32h7-uart";
reg = <0x4000f000 0x400>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
resets = <&rcc USART3_R>;
status = "disabled";
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
resets = <&rcc UART4_R>;
status = "disabled";
};
uart5: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
resets = <&rcc UART5_R>;
status = "disabled";
};
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
resets = <&rcc UART7_R>;
status = "disabled";
};
uart8: serial@40019000 {
compatible = "st,stm32h7-uart";
reg = <0x40019000 0x400>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
resets = <&rcc UART8_R>;
status = "disabled";
};
usart6: serial@44003000 {
compatible = "st,stm32h7-uart";
reg = <0x44003000 0x400>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
resets = <&rcc USART6_R>;
status = "disabled";
};
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x40000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
usb33d-supply = <&usb33>;
status = "disabled";
};
usart1: serial@4c000000 {
compatible = "st,stm32h7-uart";
reg = <0x4c000000 0x400>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
resets = <&rcc USART1_R>;
status = "disabled";
};
usart2: serial@4c001000 {
compatible = "st,stm32h7-uart";
reg = <0x4c001000 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
resets = <&rcc USART2_R>;
status = "disabled";
};
i2c3: i2c@4c004000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c004000 0x400>;
interrupt-names = "event", "error";
interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C3_K>;
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
i2c-analog-filter;
status = "disabled";
};
i2c4: i2c@4c005000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c005000 0x400>;
interrupt-names = "event", "error";
interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C4_K>;
resets = <&rcc I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
i2c-analog-filter;
status = "disabled";
};
i2c5: i2c@4c006000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c006000 0x400>;
interrupt-names = "event", "error";
interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C5_K>;
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
i2c-analog-filter;
status = "disabled";
};
rcc: rcc@50000000 {
compatible = "st,stm32mp13-rcc", "syscon";
reg = <0x50000000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
#reset-cells = <1>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
secure-interrupt-names = "wakeup";
};
pwr_regulators: pwr@50001000 {
compatible = "st,stm32mp1,pwr-reg";
reg = <0x50001000 0x10>;
reg11: reg11 {
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
reg18: reg18 {
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
usb33: usb33 {
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
};
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;
};
vrefbuf: vrefbuf@50025000 {
compatible = "st,stm32-vrefbuf";
reg = <0x50025000 0x8>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2500000>;
clocks = <&rcc VREF>;
status = "disabled";
};
hash: hash@54003000 {
compatible = "st,stm32mp13-hash";
reg = <0x54003000 0x400>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
status = "disabled";
};
rng: rng@54004000 {
compatible = "st,stm32mp13-rng";
reg = <0x54004000 0x400>;
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
status = "disabled";
};
fmc: memory-controller@58002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
nand-controller@4,0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
<4 0x08020000 0x1000>,
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
qspi: spi@58003000 {
compatible = "st,stm32f469-qspi";
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
status = "disabled";
};
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
sdmmc2: mmc@58007000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
crc1: crc@58009000 {
compatible = "st,stm32f7-crc";
reg = <0x58009000 0x400>;
clocks = <&rcc CRC1>;
};
usbh_ohci: usbh-ohci@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
usbh_ehci: usbh-ehci@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
status = "disabled";
};
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
ddr: ddr@5a003000{
compatible = "st,stm32mp13-ddr";
reg = <0x5a003000 0x550>, <0x5a004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
};
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
status = "disabled";
usbphyc_port0: usb-phy@0 {
#phy-cells = <0>;
reg = <0>;
};
usbphyc_port1: usb-phy@1 {
#phy-cells = <1>;
reg = <1>;
};
};
iwdg1: watchdog@5c003000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5c003000 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
bsec: efuse@5c005000 {
compatible = "st,stm32mp15-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
cfg0_otp: cfg0_otp@0 {
reg = <0x0 0x2>;
};
part_number_otp: part_number_otp@4 {
reg = <0x4 0x2>;
};
monotonic_otp: monotonic_otp@10 {
reg = <0x10 0x4>;
};
nand_otp: cfg9_otp@24 {
reg = <0x24 0x4>;
};
nand2_otp: cfg10_otp@28 {
reg = <0x28 0x4>;
};
uid_otp: uid_otp@34 {
reg = <0x34 0xc>;
};
hw2_otp: hw2_otp@48 {
reg = <0x48 0x4>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
pkh_otp: pkh_otp@60 {
reg = <0x60 0x20>;
};
mac_addr: mac_addr@e4 {
reg = <0xe4 0xc>;
st,non-secure-otp;
};
};
tamp: tamp@5c00a000 {
reg = <0x5c00a000 0x400>;
};
/*
* Break node order to solve dependency probe issue between
* pinctrl and exti.
*/
pinctrl: pin-controller@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp135-pinctrl";
ranges = <0 0x50002000 0x8400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@50008000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@50009000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
ngpios = <15>;
gpio-ranges = <&pinctrl 0 112 15>;
};
gpioi: gpio@5000a000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 128 8>;
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp131.dtsi"
/ {
soc {
m_can1: can@4400e000 {
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
status = "disabled";
};
m_can2: can@4400f000 {
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
status = "disabled";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp133.dtsi"
/ {
soc {
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
*/
#define DDR_SIZE 0x20000000 /* 512MB */
#include "stm32mp13-fw-config.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/dts-v1/;
#include <dt-bindings/clock/stm32mp13-clksrc.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi"
#include "stm32mp13-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
aliases {
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
serial3 = &usart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
v3v3_ao: v3v3_ao {
compatible = "regulator-fixed";
regulator-name = "v3v3_ao";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&bsec {
board_id: board_id@f0 {
reg = <0xf0 0x4>;
st,non-secure-otp;
};
};
&cpu0 {
cpu-supply = <&vddcpu>;
};
&hash {
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
status = "disabled";
secure-status = "okay";
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
status = "disabled";
secure-status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&vin>;
ldo4-supply = <&vin>;
ldo5-supply = <&vin>;
ldo6-supply = <&vin>;
vref_ddr-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&v3v3_ao>;
vddcpu: buck1 {
regulator-name = "vddcpu";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-over-current-protection;
};
vddcore: buck4 {
regulator-name = "vddcore";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_adc: ldo1 {
regulator-name = "vdd_adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_sd: ldo5 {
regulator-name = "vdd_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
v1v8_periph: ldo6 {
regulator-name = "v1v8_periph";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
};
bst_out: boost {
regulator-name = "bst_out";
};
v3v3_sw: pwr_sw2 {
regulator-name = "v3v3_sw";
regulator-active-discharge = <1>;
regulator-always-on;
};
};
};
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&nvmem_layout {
nvmem-cells = <&cfg0_otp>,
<&part_number_otp>,
<&monotonic_otp>,
<&nand_otp>,
<&nand2_otp>,
<&uid_otp>,
<&hw2_otp>,
<&pkh_otp>,
<&board_id>;
nvmem-cell-names = "cfg0_otp",
"part_number_otp",
"monotonic_otp",
"nand_otp",
"nand2_otp",
"uid_otp",
"hw2_otp",
"pkh_otp",
"board_id";
};
&pka {
secure-status = "okay";
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MLAHBS_PLL3
CLK_CKPER_HSE
CLK_RTC_LSE
CLK_SDMMC1_PLL4P
CLK_SDMMC2_PLL4P
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_I2C4_HSI
CLK_USBO_USBPHY
CLK_I2C12_HSI
CLK_UART2_HSI
CLK_UART4_HSI
CLK_SAES_AXI
>;
st,clkdiv = <
DIV(DIV_AXI, 0)
DIV(DIV_MLAHB, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_APB6, 1)
DIV(DIV_RTC, 0)
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 65 >;
frac = < 0x1400 >;
};
pll3_vco_417_8Mhz: pll2-vco-417_8Mhz {
src = < CLK_PLL3_HSE >;
divmn = < 1 33 >;
frac = < 0x1a04 >;
};
pll4_vco_600Mhz: pll2-vco-600Mhz {
src = < CLK_PLL4_HSE >;
divmn = < 1 49 >;
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1:st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 1 1 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
pll2:st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
st,pll = < &pll2_cfg1 >;
pll2_cfg1: pll2_cfg1 {
st,pll_vco = < &pll2_vco_1066Mhz >;
st,pll_div_pqr = < 1 1 0 >;
};
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */
pll3:st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
st,pll = < &pll3_cfg1 >;
pll3_cfg1: pll3_cfg1 {
st,pll_vco = < &pll3_vco_417_8Mhz >;
st,pll_div_pqr = < 1 16 1 >;
};
};
/* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */
pll4:st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
st,pll = < &pll4_cfg1 >;
pll4_cfg1: pll4_cfg1 {
st,pll_vco = < &pll4_vco_600Mhz >;
st,pll_div_pqr = < 11 59 5 >;
};
};
};
&rng {
status = "okay";
};
&saes {
secure-status = "okay";
};
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
status = "disabled";
};
&usart1 {
pinctrl-names = "default";
pinctrl-0 = <&usart1_pins_a>;
uart-has-rtscts;
status = "disabled";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp13xa.dtsi"
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
saes: saes@54005000 {
compatible = "st,stm32-saes";
reg = <0x54005000 0x400>;
clocks = <&rcc SAES_K>;
resets = <&rcc SAES_R>;
status = "disabled";
};
pka: pka@54006000 {
compatible = "st,stm32-pka64";
reg = <0x54006000 0x2000>;
clocks = <&rcc PKA>;
resets = <&rcc PKA_R>;
status = "disabled";
};
};
};

5
fdts/stm32mp13xd.dtsi Normal file
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@ -0,0 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

35
fdts/stm32mp13xf.dtsi Normal file
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@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp13xd.dtsi"
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
saes: saes@54005000 {
compatible = "st,stm32-saes";
reg = <0x54005000 0x400>;
clocks = <&rcc SAES_K>;
resets = <&rcc SAES_R>;
status = "disabled";
};
pka: pka@54006000 {
compatible = "st,stm32-pka64";
reg = <0x54006000 0x2000>;
clocks = <&rcc PKA>;
resets = <&rcc PKA_R>;
status = "disabled";
};
};
};

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include/drivers/st/stm32mp13_rcc.h Normal file
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2328
include/drivers/st/stm32mp15_rcc.h Normal file
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2330
include/drivers/st/stm32mp1_rcc.h
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9
include/drivers/st/stm32mp_pmic.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -48,4 +48,11 @@ static inline void print_pmic_info_and_debug(void)
*/
int pmic_ddr_power_init(enum ddr_type ddr_type);
/*
* pmic_voltages_init - Update voltages for platform init
*
* Returns 0 on success, and negative values on errors
*/
int pmic_voltages_init(void);
#endif /* STM32MP_PMIC_H */

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include/dt-bindings/clock/stm32mp1-clks.h
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@ -1,278 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
#define _DT_BINDINGS_STM32MP1_CLKS_H_
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* Bus clocks */
#define TIM2 6
#define TIM3 7
#define TIM4 8
#define TIM5 9
#define TIM6 10
#define TIM7 11
#define TIM12 12
#define TIM13 13
#define TIM14 14
#define LPTIM1 15
#define SPI2 16
#define SPI3 17
#define USART2 18
#define USART3 19
#define UART4 20
#define UART5 21
#define UART7 22
#define UART8 23
#define I2C1 24
#define I2C2 25
#define I2C3 26
#define I2C5 27
#define SPDIF 28
#define CEC 29
#define DAC12 30
#define MDIO 31
#define TIM1 32
#define TIM8 33
#define TIM15 34
#define TIM16 35
#define TIM17 36
#define SPI1 37
#define SPI4 38
#define SPI5 39
#define USART6 40
#define SAI1 41
#define SAI2 42
#define SAI3 43
#define DFSDM 44
#define FDCAN 45
#define LPTIM2 46
#define LPTIM3 47
#define LPTIM4 48
#define LPTIM5 49
#define SAI4 50
#define SYSCFG 51
#define VREF 52
#define TMPSENS 53
#define PMBCTRL 54
#define HDP 55
#define LTDC 56
#define DSI 57
#define IWDG2 58
#define USBPHY 59
#define STGENRO 60
#define SPI6 61
#define I2C4 62
#define I2C6 63
#define USART1 64
#define RTCAPB 65
#define TZC1 66
#define TZPC 67
#define IWDG1 68
#define BSEC 69
#define STGEN 70
#define DMA1 71
#define DMA2 72
#define DMAMUX 73
#define ADC12 74
#define USBO 75
#define SDMMC3 76
#define DCMI 77
#define CRYP2 78
#define HASH2 79
#define RNG2 80
#define CRC2 81
#define HSEM 82
#define IPCC 83
#define GPIOA 84
#define GPIOB 85
#define GPIOC 86
#define GPIOD 87
#define GPIOE 88
#define GPIOF 89
#define GPIOG 90
#define GPIOH 91
#define GPIOI 92
#define GPIOJ 93
#define GPIOK 94
#define GPIOZ 95
#define CRYP1 96
#define HASH1 97
#define RNG1 98
#define BKPSRAM 99
#define MDMA 100
#define GPU 101
#define ETHCK 102
#define ETHTX 103
#define ETHRX 104
#define ETHMAC 105
#define FMC 106
#define QSPI 107
#define SDMMC1 108
#define SDMMC2 109
#define CRC1 110
#define USBH 111
#define ETHSTP 112
#define TZC2 113
/* Kernel clocks */
#define SDMMC1_K 118
#define SDMMC2_K 119
#define SDMMC3_K 120
#define FMC_K 121
#define QSPI_K 122
#define ETHCK_K 123
#define RNG1_K 124
#define RNG2_K 125
#define GPU_K 126
#define USBPHY_K 127
#define STGEN_K 128
#define SPDIF_K 129
#define SPI1_K 130
#define SPI2_K 131
#define SPI3_K 132
#define SPI4_K 133
#define SPI5_K 134
#define SPI6_K 135
#define CEC_K 136
#define I2C1_K 137
#define I2C2_K 138
#define I2C3_K 139
#define I2C4_K 140
#define I2C5_K 141
#define I2C6_K 142
#define LPTIM1_K 143
#define LPTIM2_K 144
#define LPTIM3_K 145
#define LPTIM4_K 146
#define LPTIM5_K 147
#define USART1_K 148
#define USART2_K 149
#define USART3_K 150
#define UART4_K 151
#define UART5_K 152
#define USART6_K 153
#define UART7_K 154
#define UART8_K 155
#define DFSDM_K 156
#define FDCAN_K 157
#define SAI1_K 158
#define SAI2_K 159
#define SAI3_K 160
#define SAI4_K 161
#define ADC12_K 162
#define DSI_K 163
#define DSI_PX 164
#define ADFSDM_K 165
#define USBO_K 166
#define LTDC_PX 167
#define DAC12_K 168
#define ETHPTP_K 169
/* PLL */
#define PLL1 176
#define PLL2 177
#define PLL3 178
#define PLL4 179
/* ODF */
#define PLL1_P 180
#define PLL1_Q 181
#define PLL1_R 182
#define PLL2_P 183
#define PLL2_Q 184
#define PLL2_R 185
#define PLL3_P 186
#define PLL3_Q 187
#define PLL3_R 188
#define PLL4_P 189
#define PLL4_Q 190
#define PLL4_R 191
/* AUX */
#define RTC 192
/* MCLK */
#define CK_PER 193
#define CK_MPU 194
#define CK_AXI 195
#define CK_MCU 196
/* Time base */
#define TIM2_K 197
#define TIM3_K 198
#define TIM4_K 199
#define TIM5_K 200
#define TIM6_K 201
#define TIM7_K 202
#define TIM12_K 203
#define TIM13_K 204
#define TIM14_K 205
#define TIM1_K 206
#define TIM8_K 207
#define TIM15_K 208
#define TIM16_K 209
#define TIM17_K 210
/* MCO clocks */
#define CK_MCO1 211
#define CK_MCO2 212
/* TRACE & DEBUG clocks */
#define CK_DBG 214
#define CK_TRACE 215
/* DDR */
#define DDRC1 220
#define DDRC1LP 221
#define DDRC2 222
#define DDRC2LP 223
#define DDRPHYC 224
#define DDRPHYCLP 225
#define DDRCAPB 226
#define DDRCAPBLP 227
#define AXIDCG 228
#define DDRPHYCAPB 229
#define DDRPHYCAPBLP 230
#define DDRPERFM 231
#define STM32MP1_LAST_CLK 232
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
#define CK_SCMI0_HSI 1
#define CK_SCMI0_CSI 2
#define CK_SCMI0_LSE 3
#define CK_SCMI0_LSI 4
#define CK_SCMI0_PLL2_Q 5
#define CK_SCMI0_PLL2_R 6
#define CK_SCMI0_MPU 7
#define CK_SCMI0_AXI 8
#define CK_SCMI0_BSEC 9
#define CK_SCMI0_CRYP1 10
#define CK_SCMI0_GPIOZ 11
#define CK_SCMI0_HASH1 12
#define CK_SCMI0_I2C4 13
#define CK_SCMI0_I2C6 14
#define CK_SCMI0_IWDG1 15
#define CK_SCMI0_RNG1 16
#define CK_SCMI0_RTC 17
#define CK_SCMI0_RTCAPB 18
#define CK_SCMI0_SPI6 19
#define CK_SCMI0_USART1 20
#define CK_SCMI1_PLL3_Q 0
#define CK_SCMI1_PLL3_R 1
#define CK_SCMI1_MCU 2
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
#if STM32MP13
#include "stm32mp13-clks.h"
#endif
#if STM32MP15
#include "stm32mp15-clks.h"
#endif

284
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@ -1,283 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
/* PLL output is enable when x=1, with x=p,q or r */
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
/* st,clksrc: mandatory clock source */
#define CLK_MPU_HSI 0x00000200
#define CLK_MPU_HSE 0x00000201
#define CLK_MPU_PLL1P 0x00000202
#define CLK_MPU_PLL1P_DIV 0x00000203
#define CLK_AXI_HSI 0x00000240
#define CLK_AXI_HSE 0x00000241
#define CLK_AXI_PLL2P 0x00000242
#define CLK_MCU_HSI 0x00000480
#define CLK_MCU_HSE 0x00000481
#define CLK_MCU_CSI 0x00000482
#define CLK_MCU_PLL3P 0x00000483
#define CLK_PLL12_HSI 0x00000280
#define CLK_PLL12_HSE 0x00000281
#define CLK_PLL3_HSI 0x00008200
#define CLK_PLL3_HSE 0x00008201
#define CLK_PLL3_CSI 0x00008202
#define CLK_PLL4_HSI 0x00008240
#define CLK_PLL4_HSE 0x00008241
#define CLK_PLL4_CSI 0x00008242
#define CLK_PLL4_I2SCKIN 0x00008243
#define CLK_RTC_DISABLED 0x00001400
#define CLK_RTC_LSE 0x00001401
#define CLK_RTC_LSI 0x00001402
#define CLK_RTC_HSE 0x00001403
#define CLK_MCO1_HSI 0x00008000
#define CLK_MCO1_HSE 0x00008001
#define CLK_MCO1_CSI 0x00008002
#define CLK_MCO1_LSI 0x00008003
#define CLK_MCO1_LSE 0x00008004
#define CLK_MCO1_DISABLED 0x0000800F
#define CLK_MCO2_MPU 0x00008040
#define CLK_MCO2_AXI 0x00008041
#define CLK_MCO2_MCU 0x00008042
#define CLK_MCO2_PLL4P 0x00008043
#define CLK_MCO2_HSE 0x00008044
#define CLK_MCO2_HSI 0x00008045
#define CLK_MCO2_DISABLED 0x0000804F
/* st,pkcs: peripheral kernel clock source */
#define CLK_I2C12_PCLK1 0x00008C00
#define CLK_I2C12_PLL4R 0x00008C01
#define CLK_I2C12_HSI 0x00008C02
#define CLK_I2C12_CSI 0x00008C03
#define CLK_I2C12_DISABLED 0x00008C07
#define CLK_I2C35_PCLK1 0x00008C40
#define CLK_I2C35_PLL4R 0x00008C41
#define CLK_I2C35_HSI 0x00008C42
#define CLK_I2C35_CSI 0x00008C43
#define CLK_I2C35_DISABLED 0x00008C47
#define CLK_I2C46_PCLK5 0x00000C00
#define CLK_I2C46_PLL3Q 0x00000C01
#define CLK_I2C46_HSI 0x00000C02
#define CLK_I2C46_CSI 0x00000C03
#define CLK_I2C46_DISABLED 0x00000C07
#define CLK_SAI1_PLL4Q 0x00008C80
#define CLK_SAI1_PLL3Q 0x00008C81
#define CLK_SAI1_I2SCKIN 0x00008C82
#define CLK_SAI1_CKPER 0x00008C83
#define CLK_SAI1_PLL3R 0x00008C84
#define CLK_SAI1_DISABLED 0x00008C87
#define CLK_SAI2_PLL4Q 0x00008CC0
#define CLK_SAI2_PLL3Q 0x00008CC1
#define CLK_SAI2_I2SCKIN 0x00008CC2
#define CLK_SAI2_CKPER 0x00008CC3
#define CLK_SAI2_SPDIF 0x00008CC4
#define CLK_SAI2_PLL3R 0x00008CC5
#define CLK_SAI2_DISABLED 0x00008CC7
#define CLK_SAI3_PLL4Q 0x00008D00
#define CLK_SAI3_PLL3Q 0x00008D01
#define CLK_SAI3_I2SCKIN 0x00008D02
#define CLK_SAI3_CKPER 0x00008D03
#define CLK_SAI3_PLL3R 0x00008D04
#define CLK_SAI3_DISABLED 0x00008D07
#define CLK_SAI4_PLL4Q 0x00008D40
#define CLK_SAI4_PLL3Q 0x00008D41
#define CLK_SAI4_I2SCKIN 0x00008D42
#define CLK_SAI4_CKPER 0x00008D43
#define CLK_SAI4_PLL3R 0x00008D44
#define CLK_SAI4_DISABLED 0x00008D47
#define CLK_SPI2S1_PLL4P 0x00008D80
#define CLK_SPI2S1_PLL3Q 0x00008D81
#define CLK_SPI2S1_I2SCKIN 0x00008D82
#define CLK_SPI2S1_CKPER 0x00008D83
#define CLK_SPI2S1_PLL3R 0x00008D84
#define CLK_SPI2S1_DISABLED 0x00008D87
#define CLK_SPI2S23_PLL4P 0x00008DC0
#define CLK_SPI2S23_PLL3Q 0x00008DC1
#define CLK_SPI2S23_I2SCKIN 0x00008DC2
#define CLK_SPI2S23_CKPER 0x00008DC3
#define CLK_SPI2S23_PLL3R 0x00008DC4
#define CLK_SPI2S23_DISABLED 0x00008DC7
#define CLK_SPI45_PCLK2 0x00008E00
#define CLK_SPI45_PLL4Q 0x00008E01
#define CLK_SPI45_HSI 0x00008E02
#define CLK_SPI45_CSI 0x00008E03
#define CLK_SPI45_HSE 0x00008E04
#define CLK_SPI45_DISABLED 0x00008E07
#define CLK_SPI6_PCLK5 0x00000C40
#define CLK_SPI6_PLL4Q 0x00000C41
#define CLK_SPI6_HSI 0x00000C42
#define CLK_SPI6_CSI 0x00000C43
#define CLK_SPI6_HSE 0x00000C44
#define CLK_SPI6_PLL3Q 0x00000C45
#define CLK_SPI6_DISABLED 0x00000C47
#define CLK_UART6_PCLK2 0x00008E40
#define CLK_UART6_PLL4Q 0x00008E41
#define CLK_UART6_HSI 0x00008E42
#define CLK_UART6_CSI 0x00008E43
#define CLK_UART6_HSE 0x00008E44
#define CLK_UART6_DISABLED 0x00008E47
#define CLK_UART24_PCLK1 0x00008E80
#define CLK_UART24_PLL4Q 0x00008E81
#define CLK_UART24_HSI 0x00008E82
#define CLK_UART24_CSI 0x00008E83
#define CLK_UART24_HSE 0x00008E84
#define CLK_UART24_DISABLED 0x00008E87
#define CLK_UART35_PCLK1 0x00008EC0
#define CLK_UART35_PLL4Q 0x00008EC1
#define CLK_UART35_HSI 0x00008EC2
#define CLK_UART35_CSI 0x00008EC3
#define CLK_UART35_HSE 0x00008EC4
#define CLK_UART35_DISABLED 0x00008EC7
#define CLK_UART78_PCLK1 0x00008F00
#define CLK_UART78_PLL4Q 0x00008F01
#define CLK_UART78_HSI 0x00008F02
#define CLK_UART78_CSI 0x00008F03
#define CLK_UART78_HSE 0x00008F04
#define CLK_UART78_DISABLED 0x00008F07
#define CLK_UART1_PCLK5 0x00000C80
#define CLK_UART1_PLL3Q 0x00000C81
#define CLK_UART1_HSI 0x00000C82
#define CLK_UART1_CSI 0x00000C83
#define CLK_UART1_PLL4Q 0x00000C84
#define CLK_UART1_HSE 0x00000C85
#define CLK_UART1_DISABLED 0x00000C87
#define CLK_SDMMC12_HCLK6 0x00008F40
#define CLK_SDMMC12_PLL3R 0x00008F41
#define CLK_SDMMC12_PLL4P 0x00008F42
#define CLK_SDMMC12_HSI 0x00008F43
#define CLK_SDMMC12_DISABLED 0x00008F47
#define CLK_SDMMC3_HCLK2 0x00008F80
#define CLK_SDMMC3_PLL3R 0x00008F81
#define CLK_SDMMC3_PLL4P 0x00008F82
#define CLK_SDMMC3_HSI 0x00008F83
#define CLK_SDMMC3_DISABLED 0x00008F87
#define CLK_ETH_PLL4P 0x00008FC0
#define CLK_ETH_PLL3Q 0x00008FC1
#define CLK_ETH_DISABLED 0x00008FC3
#define CLK_QSPI_ACLK 0x00009000
#define CLK_QSPI_PLL3R 0x00009001
#define CLK_QSPI_PLL4P 0x00009002
#define CLK_QSPI_CKPER 0x00009003
#define CLK_FMC_ACLK 0x00009040
#define CLK_FMC_PLL3R 0x00009041
#define CLK_FMC_PLL4P 0x00009042
#define CLK_FMC_CKPER 0x00009043
#define CLK_FDCAN_HSE 0x000090C0
#define CLK_FDCAN_PLL3Q 0x000090C1
#define CLK_FDCAN_PLL4Q 0x000090C2
#define CLK_FDCAN_PLL4R 0x000090C3
#define CLK_SPDIF_PLL4P 0x00009140
#define CLK_SPDIF_PLL3Q 0x00009141
#define CLK_SPDIF_HSI 0x00009142
#define CLK_SPDIF_DISABLED 0x00009143
#define CLK_CEC_LSE 0x00009180
#define CLK_CEC_LSI 0x00009181
#define CLK_CEC_CSI_DIV122 0x00009182
#define CLK_CEC_DISABLED 0x00009183
#define CLK_USBPHY_HSE 0x000091C0
#define CLK_USBPHY_PLL4R 0x000091C1
#define CLK_USBPHY_HSE_DIV2 0x000091C2
#define CLK_USBPHY_DISABLED 0x000091C3
#define CLK_USBO_PLL4R 0x800091C0
#define CLK_USBO_USBPHY 0x800091C1
#define CLK_RNG1_CSI 0x00000CC0
#define CLK_RNG1_PLL4R 0x00000CC1
#define CLK_RNG1_LSE 0x00000CC2
#define CLK_RNG1_LSI 0x00000CC3
#define CLK_RNG2_CSI 0x00009200
#define CLK_RNG2_PLL4R 0x00009201
#define CLK_RNG2_LSE 0x00009202
#define CLK_RNG2_LSI 0x00009203
#define CLK_CKPER_HSI 0x00000D00
#define CLK_CKPER_CSI 0x00000D01
#define CLK_CKPER_HSE 0x00000D02
#define CLK_CKPER_DISABLED 0x00000D03
#define CLK_STGEN_HSI 0x00000D40
#define CLK_STGEN_HSE 0x00000D41
#define CLK_STGEN_DISABLED 0x00000D43
#define CLK_DSI_DSIPLL 0x00009240
#define CLK_DSI_PLL4P 0x00009241
#define CLK_ADC_PLL4R 0x00009280
#define CLK_ADC_CKPER 0x00009281
#define CLK_ADC_PLL3Q 0x00009282
#define CLK_ADC_DISABLED 0x00009283
#define CLK_LPTIM45_PCLK3 0x000092C0
#define CLK_LPTIM45_PLL4P 0x000092C1
#define CLK_LPTIM45_PLL3Q 0x000092C2
#define CLK_LPTIM45_LSE 0x000092C3
#define CLK_LPTIM45_LSI 0x000092C4
#define CLK_LPTIM45_CKPER 0x000092C5
#define CLK_LPTIM45_DISABLED 0x000092C7
#define CLK_LPTIM23_PCLK3 0x00009300
#define CLK_LPTIM23_PLL4Q 0x00009301
#define CLK_LPTIM23_CKPER 0x00009302
#define CLK_LPTIM23_LSE 0x00009303
#define CLK_LPTIM23_LSI 0x00009304
#define CLK_LPTIM23_DISABLED 0x00009307
#define CLK_LPTIM1_PCLK1 0x00009340
#define CLK_LPTIM1_PLL4P 0x00009341
#define CLK_LPTIM1_PLL3Q 0x00009342
#define CLK_LPTIM1_LSE 0x00009343
#define CLK_LPTIM1_LSI 0x00009344
#define CLK_LPTIM1_CKPER 0x00009345
#define CLK_LPTIM1_DISABLED 0x00009347
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#if STM32MP13
#include "stm32mp13-clksrc.h"
#endif
#if STM32MP15
#include "stm32mp15-clksrc.h"
#endif

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/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_
#define _DT_BINDINGS_STM32MP13_CLKS_H_
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* PLL */
#define PLL1 6
#define PLL2 7
#define PLL3 8
#define PLL4 9
/* ODF */
#define PLL1_P 10
#define PLL1_Q 11
#define PLL1_R 12
#define PLL2_P 13
#define PLL2_Q 14
#define PLL2_R 15
#define PLL3_P 16
#define PLL3_Q 17
#define PLL3_R 18
#define PLL4_P 19
#define PLL4_Q 20
#define PLL4_R 21
#define PCLK1 22
#define PCLK2 23
#define PCLK3 24
#define PCLK4 25
#define PCLK5 26
#define PCLK6 27
/* SYSTEM CLOCK */
#define CK_PER 28
#define CK_MPU 29
#define CK_AXI 30
#define CK_MLAHB 31
/* BASE TIMER */
#define CK_TIMG1 32
#define CK_TIMG2 33
#define CK_TIMG3 34
/* AUX */
#define RTC 35
/* TRACE & DEBUG clocks */
#define CK_DBG 36
#define CK_TRACE 37
/* MCO clocks */
#define CK_MCO1 38
#define CK_MCO2 39
/* IP clocks */
#define SYSCFG 40
#define VREF 41
#define TMPSENS 42
#define PMBCTRL 43
#define HDP 44
#define IWDG2 45
#define STGENRO 46
#define USART1 47
#define RTCAPB 48
#define TZC 49
#define TZPC 50
#define IWDG1 51
#define BSEC 52
#define DMA1 53
#define DMA2 54
#define DMAMUX1 55
#define DMAMUX2 56
#define GPIOA 57
#define GPIOB 58
#define GPIOC 59
#define GPIOD 60
#define GPIOE 61
#define GPIOF 62
#define GPIOG 63
#define GPIOH 64
#define GPIOI 65
#define CRYP1 66
#define HASH1 67
#define BKPSRAM 68
#define MDMA 69
#define CRC1 70
#define USBH 71
#define DMA3 72
#define TSC 73
#define PKA 74
#define AXIMC 75
#define MCE 76
#define ETH1TX 77
#define ETH2TX 78
#define ETH1RX 79
#define ETH2RX 80
#define ETH1MAC 81
#define ETH2MAC 82
#define ETH1STP 83
#define ETH2STP 84
/* IP clocks with parents */
#define SDMMC1_K 85
#define SDMMC2_K 86
#define ADC1_K 87
#define ADC2_K 88
#define FMC_K 89
#define QSPI_K 90
#define RNG1_K 91
#define USBPHY_K 92
#define STGEN_K 93
#define SPDIF_K 94
#define SPI1_K 95
#define SPI2_K 96
#define SPI3_K 97
#define SPI4_K 98
#define SPI5_K 99
#define I2C1_K 100
#define I2C2_K 101
#define I2C3_K 102
#define I2C4_K 103
#define I2C5_K 104
#define TIM2_K 105
#define TIM3_K 106
#define TIM4_K 107
#define TIM5_K 108
#define TIM6_K 109
#define TIM7_K 110
#define TIM12_K 111
#define TIM13_K 112
#define TIM14_K 113
#define TIM1_K 114
#define TIM8_K 115
#define TIM15_K 116
#define TIM16_K 117
#define TIM17_K 118
#define LPTIM1_K 119
#define LPTIM2_K 120
#define LPTIM3_K 121
#define LPTIM4_K 122
#define LPTIM5_K 123
#define USART1_K 124
#define USART2_K 125
#define USART3_K 126
#define UART4_K 127
#define UART5_K 128
#define USART6_K 129
#define UART7_K 130
#define UART8_K 131
#define DFSDM_K 132
#define FDCAN_K 133
#define SAI1_K 134
#define SAI2_K 135
#define ADFSDM_K 136
#define USBO_K 137
#define LTDC_PX 138
#define ETH1CK_K 139
#define ETH1PTP_K 140
#define ETH2CK_K 141
#define ETH2PTP_K 142
#define DCMIPP_K 143
#define SAES_K 144
#define DTS_K 145
/* DDR */
#define DDRC1 146
#define DDRC1LP 147
#define DDRC2 148
#define DDRC2LP 149
#define DDRPHYC 150
#define DDRPHYCLP 151
#define DDRCAPB 152
#define DDRCAPBLP 153
#define AXIDCG 154
#define DDRPHYCAPB 155
#define DDRPHYCAPBLP 156
#define DDRPERFM 157
#define ADC1 158
#define ADC2 159
#define SAI1 160
#define SAI2 161
#define STM32MP1_LAST_CLK 162
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
#define CK_SCMI0_HSI 1
#define CK_SCMI0_CSI 2
#define CK_SCMI0_LSE 3
#define CK_SCMI0_LSI 4
#define CK_SCMI0_HSE_DIV2 5
#define CK_SCMI0_PLL2_Q 6
#define CK_SCMI0_PLL2_R 7
#define CK_SCMI0_PLL3_P 8
#define CK_SCMI0_PLL3_Q 9
#define CK_SCMI0_PLL3_R 10
#define CK_SCMI0_PLL4_P 11
#define CK_SCMI0_PLL4_Q 12
#define CK_SCMI0_PLL4_R 13
#define CK_SCMI0_MPU 14
#define CK_SCMI0_AXI 15
#define CK_SCMI0_MLAHB 16
#define CK_SCMI0_CKPER 17
#define CK_SCMI0_PCLK1 18
#define CK_SCMI0_PCLK2 19
#define CK_SCMI0_PCLK3 20
#define CK_SCMI0_PCLK4 21
#define CK_SCMI0_PCLK5 22
#define CK_SCMI0_PCLK6 23
#define CK_SCMI0_CKTIMG1 24
#define CK_SCMI0_CKTIMG2 25
#define CK_SCMI0_CKTIMG3 26
#define CK_SCMI0_RTC 27
#define CK_SCMI0_RTCAPB 28
#define CK_SCMI0_BSEC 29
#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */

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/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_
#define CMD_DIV 0
#define CMD_MUX 1
#define CMD_CLK 2
#define CMD_RESERVED1 3
#define CMD_SHIFT 26
#define CMD_MASK 0xFC000000
#define CMD_DATA_MASK 0x03FFFFFF
#define DIV_ID_SHIFT 8
#define DIV_ID_MASK 0x0000FF00
#define DIV_DIVN_SHIFT 0
#define DIV_DIVN_MASK 0x000000FF
#define MUX_ID_SHIFT 4
#define MUX_ID_MASK 0x00000FF0
#define MUX_SEL_SHIFT 0
#define MUX_SEL_MASK 0x0000000F
#define CLK_ID_MASK GENMASK_32(19, 11)
#define CLK_ID_SHIFT 11
#define CLK_ON_MASK 0x00000400
#define CLK_ON_SHIFT 10
#define CLK_DIV_MASK GENMASK_32(9, 4)
#define CLK_DIV_SHIFT 4
#define CLK_SEL_MASK GENMASK_32(3, 0)
#define CLK_SEL_SHIFT 0
#define DIV_PLL1DIVP 0
#define DIV_PLL2DIVP 1
#define DIV_PLL2DIVQ 2
#define DIV_PLL2DIVR 3
#define DIV_PLL3DIVP 4
#define DIV_PLL3DIVQ 5
#define DIV_PLL3DIVR 6
#define DIV_PLL4DIVP 7
#define DIV_PLL4DIVQ 8
#define DIV_PLL4DIVR 9
#define DIV_MPU 10
#define DIV_AXI 11
#define DIV_MLAHB 12
#define DIV_APB1 13
#define DIV_APB2 14
#define DIV_APB3 15
#define DIV_APB4 16
#define DIV_APB5 17
#define DIV_APB6 18
#define DIV_RTC 19
#define DIV_MCO1 20
#define DIV_MCO2 21
#define DIV_HSI 22
#define DIV_TRACE 23
#define DIV_ETH1PTP 24
#define DIV_ETH2PTP 25
#define DIV_MAX 26
#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
((div_id) << DIV_ID_SHIFT |\
(div)))
#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
((mux_id) << MUX_ID_SHIFT |\
(sel)))
/* MCO output is enable */
#define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\
(((mco_id) << CLK_ID_SHIFT) |\
(sel)) | CLK_ON_MASK)
#define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\
((mco_id) << CLK_ID_SHIFT))
/* CLK output is enable */
#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\
(((clk_id) << CLK_ID_SHIFT) |\
(sel)) | CLK_ON_MASK)
#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\
((clk_id) << CLK_ID_SHIFT))
#define MUX_MPU 0
#define MUX_AXI 1
#define MUX_MLAHB 2
#define MUX_PLL12 3
#define MUX_PLL3 4
#define MUX_PLL4 5
#define MUX_RTC 6
#define MUX_MCO1 7
#define MUX_MCO2 8
#define MUX_CKPER 9
#define MUX_KERNEL_BEGIN 10
#define MUX_ADC1 10
#define MUX_ADC2 11
#define MUX_DCMIPP 12
#define MUX_ETH1 13
#define MUX_ETH2 14
#define MUX_FDCAN 15
#define MUX_FMC 16
#define MUX_I2C12 17
#define MUX_I2C3 18
#define MUX_I2C4 19
#define MUX_I2C5 20
#define MUX_LPTIM1 21
#define MUX_LPTIM2 22
#define MUX_LPTIM3 23
#define MUX_LPTIM45 24
#define MUX_QSPI 25
#define MUX_RNG1 26
#define MUX_SAES 27
#define MUX_SAI1 28
#define MUX_SAI2 29
#define MUX_SDMMC1 30
#define MUX_SDMMC2 31
#define MUX_SPDIF 32
#define MUX_SPI1 33
#define MUX_SPI23 34
#define MUX_SPI4 35
#define MUX_SPI5 36
#define MUX_STGEN 37
#define MUX_UART1 38
#define MUX_UART2 39
#define MUX_UART35 40
#define MUX_UART4 41
#define MUX_UART6 42
#define MUX_UART78 43
#define MUX_USBO 44
#define MUX_USBPHY 45
#define MUX_MAX 46
#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0)
#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1)
#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2)
#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3)
#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0)
#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1)
#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2)
#define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0)
#define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1)
#define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2)
#define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3)
#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0)
#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1)
#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0)
#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2)
#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0)
#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1)
#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2)
#define CLK_RTC_DISABLED CLK_DISABLED(RTC)
#define CLK_RTC_LSE CLK_SRC(RTC, 1)
#define CLK_RTC_LSI CLK_SRC(RTC, 2)
#define CLK_RTC_HSE CLK_SRC(RTC, 3)
#define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0)
#define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1)
#define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2)
#define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3)
#define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4)
#define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1)
#define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0)
#define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1)
#define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2)
#define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3)
#define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4)
#define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5)
#define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2)
#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0)
#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1)
#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2)
#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3)
#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0)
#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1)
#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2)
#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3)
#define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0)
#define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1)
#define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2)
#define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3)
#define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0)
#define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1)
#define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2)
#define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3)
#define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0)
#define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1)
#define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2)
#define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3)
#define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0)
#define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1)
#define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2)
#define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3)
#define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4)
#define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0)
#define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1)
#define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2)
#define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3)
#define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4)
#define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0)
#define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1)
#define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2)
#define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3)
#define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4)
#define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5)
#define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0)
#define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1)
#define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2)
#define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3)
#define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4)
#define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0)
#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1)
#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2)
#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3)
#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4)
#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5)
#define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0)
#define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1)
#define CLK_UART2_HSI CLKSRC(MUX_UART2, 2)
#define CLK_UART2_CSI CLKSRC(MUX_UART2, 3)
#define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4)
#define CLK_UART2_HSE CLKSRC(MUX_UART2, 5)
#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0)
#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1)
#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2)
#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3)
#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4)
#define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0)
#define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1)
#define CLK_UART4_HSI CLKSRC(MUX_UART4, 2)
#define CLK_UART4_CSI CLKSRC(MUX_UART4, 3)
#define CLK_UART4_HSE CLKSRC(MUX_UART4, 4)
#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0)
#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1)
#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2)
#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3)
#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4)
#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0)
#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1)
#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2)
#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3)
#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4)
#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0)
#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1)
#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2)
#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3)
#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4)
#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5)
#define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0)
#define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1)
#define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2)
#define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3)
#define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4)
#define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0)
#define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1)
#define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2)
#define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3)
#define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4)
#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0)
#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1)
#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2)
#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3)
#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4)
#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5)
#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0)
#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1)
#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2)
#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3)
#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4)
#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0)
#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1)
#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2)
#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3)
#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4)
#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5)
#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0)
#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1)
#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2)
#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3)
#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0)
#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1)
#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2)
#define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0)
#define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1)
#define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2)
#define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0)
#define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1)
#define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2)
#define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0)
#define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1)
#define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2)
#define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3)
#define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0)
#define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1)
#define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2)
#define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3)
#define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0)
#define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1)
#define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0)
#define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1)
#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0)
#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1)
#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2)
#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0)
#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1)
#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0)
#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1)
#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2)
#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3)
#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0)
#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1)
#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2)
#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3)
#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0)
#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1)
/* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */
#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3)
#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0)
#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1)
#define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0)
#define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1)
#define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2)
#define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3)
#define CLK_SAES_AXI CLKSRC(MUX_SAES, 0)
#define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1)
#define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2)
#define CLK_SAES_LSI CLKSRC(MUX_SAES, 3)
/* PLL output is enable when x=1, with x=p,q or r */
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#endif /* _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ */

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/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
#define _DT_BINDINGS_STM32MP1_CLKS_H_
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* Bus clocks */
#define TIM2 6
#define TIM3 7
#define TIM4 8
#define TIM5 9
#define TIM6 10
#define TIM7 11
#define TIM12 12
#define TIM13 13
#define TIM14 14
#define LPTIM1 15
#define SPI2 16
#define SPI3 17
#define USART2 18
#define USART3 19
#define UART4 20
#define UART5 21
#define UART7 22
#define UART8 23
#define I2C1 24
#define I2C2 25
#define I2C3 26
#define I2C5 27
#define SPDIF 28
#define CEC 29
#define DAC12 30
#define MDIO 31
#define TIM1 32
#define TIM8 33
#define TIM15 34
#define TIM16 35
#define TIM17 36
#define SPI1 37
#define SPI4 38
#define SPI5 39
#define USART6 40
#define SAI1 41
#define SAI2 42
#define SAI3 43
#define DFSDM 44
#define FDCAN 45
#define LPTIM2 46
#define LPTIM3 47
#define LPTIM4 48
#define LPTIM5 49
#define SAI4 50
#define SYSCFG 51
#define VREF 52
#define TMPSENS 53
#define PMBCTRL 54
#define HDP 55
#define LTDC 56
#define DSI 57
#define IWDG2 58
#define USBPHY 59
#define STGENRO 60
#define SPI6 61
#define I2C4 62
#define I2C6 63
#define USART1 64
#define RTCAPB 65
#define TZC1 66
#define TZPC 67
#define IWDG1 68
#define BSEC 69
#define STGEN 70
#define DMA1 71
#define DMA2 72
#define DMAMUX 73
#define ADC12 74
#define USBO 75
#define SDMMC3 76
#define DCMI 77
#define CRYP2 78
#define HASH2 79
#define RNG2 80
#define CRC2 81
#define HSEM 82
#define IPCC 83
#define GPIOA 84
#define GPIOB 85
#define GPIOC 86
#define GPIOD 87
#define GPIOE 88
#define GPIOF 89
#define GPIOG 90
#define GPIOH 91
#define GPIOI 92
#define GPIOJ 93
#define GPIOK 94
#define GPIOZ 95
#define CRYP1 96
#define HASH1 97
#define RNG1 98
#define BKPSRAM 99
#define MDMA 100
#define GPU 101
#define ETHCK 102
#define ETHTX 103
#define ETHRX 104
#define ETHMAC 105
#define FMC 106
#define QSPI 107
#define SDMMC1 108
#define SDMMC2 109
#define CRC1 110
#define USBH 111
#define ETHSTP 112
#define TZC2 113
/* Kernel clocks */
#define SDMMC1_K 118
#define SDMMC2_K 119
#define SDMMC3_K 120
#define FMC_K 121
#define QSPI_K 122
#define ETHCK_K 123
#define RNG1_K 124
#define RNG2_K 125
#define GPU_K 126
#define USBPHY_K 127
#define STGEN_K 128
#define SPDIF_K 129
#define SPI1_K 130
#define SPI2_K 131
#define SPI3_K 132
#define SPI4_K 133
#define SPI5_K 134
#define SPI6_K 135
#define CEC_K 136
#define I2C1_K 137
#define I2C2_K 138
#define I2C3_K 139
#define I2C4_K 140
#define I2C5_K 141
#define I2C6_K 142
#define LPTIM1_K 143
#define LPTIM2_K 144
#define LPTIM3_K 145
#define LPTIM4_K 146
#define LPTIM5_K 147
#define USART1_K 148
#define USART2_K 149
#define USART3_K 150
#define UART4_K 151
#define UART5_K 152
#define USART6_K 153
#define UART7_K 154
#define UART8_K 155
#define DFSDM_K 156
#define FDCAN_K 157
#define SAI1_K 158
#define SAI2_K 159
#define SAI3_K 160
#define SAI4_K 161
#define ADC12_K 162
#define DSI_K 163
#define DSI_PX 164
#define ADFSDM_K 165
#define USBO_K 166
#define LTDC_PX 167
#define DAC12_K 168
#define ETHPTP_K 169
/* PLL */
#define PLL1 176
#define PLL2 177
#define PLL3 178
#define PLL4 179
/* ODF */
#define PLL1_P 180
#define PLL1_Q 181
#define PLL1_R 182
#define PLL2_P 183
#define PLL2_Q 184
#define PLL2_R 185
#define PLL3_P 186
#define PLL3_Q 187
#define PLL3_R 188
#define PLL4_P 189
#define PLL4_Q 190
#define PLL4_R 191
/* AUX */
#define RTC 192
/* MCLK */
#define CK_PER 193
#define CK_MPU 194
#define CK_AXI 195
#define CK_MCU 196
/* Time base */
#define TIM2_K 197
#define TIM3_K 198
#define TIM4_K 199
#define TIM5_K 200
#define TIM6_K 201
#define TIM7_K 202
#define TIM12_K 203
#define TIM13_K 204
#define TIM14_K 205
#define TIM1_K 206
#define TIM8_K 207
#define TIM15_K 208
#define TIM16_K 209
#define TIM17_K 210
/* MCO clocks */
#define CK_MCO1 211
#define CK_MCO2 212
/* TRACE & DEBUG clocks */
#define CK_DBG 214
#define CK_TRACE 215
/* DDR */
#define DDRC1 220
#define DDRC1LP 221
#define DDRC2 222
#define DDRC2LP 223
#define DDRPHYC 224
#define DDRPHYCLP 225
#define DDRCAPB 226
#define DDRCAPBLP 227
#define AXIDCG 228
#define DDRPHYCAPB 229
#define DDRPHYCAPBLP 230
#define DDRPERFM 231
#define STM32MP1_LAST_CLK 232
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
#define CK_SCMI0_HSI 1
#define CK_SCMI0_CSI 2
#define CK_SCMI0_LSE 3
#define CK_SCMI0_LSI 4
#define CK_SCMI0_PLL2_Q 5
#define CK_SCMI0_PLL2_R 6
#define CK_SCMI0_MPU 7
#define CK_SCMI0_AXI 8
#define CK_SCMI0_BSEC 9
#define CK_SCMI0_CRYP1 10
#define CK_SCMI0_GPIOZ 11
#define CK_SCMI0_HASH1 12
#define CK_SCMI0_I2C4 13
#define CK_SCMI0_I2C6 14
#define CK_SCMI0_IWDG1 15
#define CK_SCMI0_RNG1 16
#define CK_SCMI0_RTC 17
#define CK_SCMI0_RTCAPB 18
#define CK_SCMI0_SPI6 19
#define CK_SCMI0_USART1 20
#define CK_SCMI1_PLL3_Q 0
#define CK_SCMI1_PLL3_R 1
#define CK_SCMI1_MCU 2
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */

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/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_
/* PLL output is enable when x=1, with x=p,q or r */
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
/* st,clksrc: mandatory clock source */
#define CLK_MPU_HSI 0x00000200
#define CLK_MPU_HSE 0x00000201
#define CLK_MPU_PLL1P 0x00000202
#define CLK_MPU_PLL1P_DIV 0x00000203
#define CLK_AXI_HSI 0x00000240
#define CLK_AXI_HSE 0x00000241
#define CLK_AXI_PLL2P 0x00000242
#define CLK_MCU_HSI 0x00000480
#define CLK_MCU_HSE 0x00000481
#define CLK_MCU_CSI 0x00000482
#define CLK_MCU_PLL3P 0x00000483
#define CLK_PLL12_HSI 0x00000280
#define CLK_PLL12_HSE 0x00000281
#define CLK_PLL3_HSI 0x00008200
#define CLK_PLL3_HSE 0x00008201
#define CLK_PLL3_CSI 0x00008202
#define CLK_PLL4_HSI 0x00008240
#define CLK_PLL4_HSE 0x00008241
#define CLK_PLL4_CSI 0x00008242
#define CLK_PLL4_I2SCKIN 0x00008243
#define CLK_RTC_DISABLED 0x00001400
#define CLK_RTC_LSE 0x00001401
#define CLK_RTC_LSI 0x00001402
#define CLK_RTC_HSE 0x00001403
#define CLK_MCO1_HSI 0x00008000
#define CLK_MCO1_HSE 0x00008001
#define CLK_MCO1_CSI 0x00008002
#define CLK_MCO1_LSI 0x00008003
#define CLK_MCO1_LSE 0x00008004
#define CLK_MCO1_DISABLED 0x0000800F
#define CLK_MCO2_MPU 0x00008040
#define CLK_MCO2_AXI 0x00008041
#define CLK_MCO2_MCU 0x00008042
#define CLK_MCO2_PLL4P 0x00008043
#define CLK_MCO2_HSE 0x00008044
#define CLK_MCO2_HSI 0x00008045
#define CLK_MCO2_DISABLED 0x0000804F
/* st,pkcs: peripheral kernel clock source */
#define CLK_I2C12_PCLK1 0x00008C00
#define CLK_I2C12_PLL4R 0x00008C01
#define CLK_I2C12_HSI 0x00008C02
#define CLK_I2C12_CSI 0x00008C03
#define CLK_I2C12_DISABLED 0x00008C07
#define CLK_I2C35_PCLK1 0x00008C40
#define CLK_I2C35_PLL4R 0x00008C41
#define CLK_I2C35_HSI 0x00008C42
#define CLK_I2C35_CSI 0x00008C43
#define CLK_I2C35_DISABLED 0x00008C47
#define CLK_I2C46_PCLK5 0x00000C00
#define CLK_I2C46_PLL3Q 0x00000C01
#define CLK_I2C46_HSI 0x00000C02
#define CLK_I2C46_CSI 0x00000C03
#define CLK_I2C46_DISABLED 0x00000C07
#define CLK_SAI1_PLL4Q 0x00008C80
#define CLK_SAI1_PLL3Q 0x00008C81
#define CLK_SAI1_I2SCKIN 0x00008C82
#define CLK_SAI1_CKPER 0x00008C83
#define CLK_SAI1_PLL3R 0x00008C84
#define CLK_SAI1_DISABLED 0x00008C87
#define CLK_SAI2_PLL4Q 0x00008CC0
#define CLK_SAI2_PLL3Q 0x00008CC1
#define CLK_SAI2_I2SCKIN 0x00008CC2
#define CLK_SAI2_CKPER 0x00008CC3
#define CLK_SAI2_SPDIF 0x00008CC4
#define CLK_SAI2_PLL3R 0x00008CC5
#define CLK_SAI2_DISABLED 0x00008CC7
#define CLK_SAI3_PLL4Q 0x00008D00
#define CLK_SAI3_PLL3Q 0x00008D01
#define CLK_SAI3_I2SCKIN 0x00008D02
#define CLK_SAI3_CKPER 0x00008D03
#define CLK_SAI3_PLL3R 0x00008D04
#define CLK_SAI3_DISABLED 0x00008D07
#define CLK_SAI4_PLL4Q 0x00008D40
#define CLK_SAI4_PLL3Q 0x00008D41
#define CLK_SAI4_I2SCKIN 0x00008D42
#define CLK_SAI4_CKPER 0x00008D43
#define CLK_SAI4_PLL3R 0x00008D44
#define CLK_SAI4_DISABLED 0x00008D47
#define CLK_SPI2S1_PLL4P 0x00008D80
#define CLK_SPI2S1_PLL3Q 0x00008D81
#define CLK_SPI2S1_I2SCKIN 0x00008D82
#define CLK_SPI2S1_CKPER 0x00008D83
#define CLK_SPI2S1_PLL3R 0x00008D84
#define CLK_SPI2S1_DISABLED 0x00008D87
#define CLK_SPI2S23_PLL4P 0x00008DC0
#define CLK_SPI2S23_PLL3Q 0x00008DC1
#define CLK_SPI2S23_I2SCKIN 0x00008DC2
#define CLK_SPI2S23_CKPER 0x00008DC3
#define CLK_SPI2S23_PLL3R 0x00008DC4
#define CLK_SPI2S23_DISABLED 0x00008DC7
#define CLK_SPI45_PCLK2 0x00008E00
#define CLK_SPI45_PLL4Q 0x00008E01
#define CLK_SPI45_HSI 0x00008E02
#define CLK_SPI45_CSI 0x00008E03
#define CLK_SPI45_HSE 0x00008E04
#define CLK_SPI45_DISABLED 0x00008E07
#define CLK_SPI6_PCLK5 0x00000C40
#define CLK_SPI6_PLL4Q 0x00000C41
#define CLK_SPI6_HSI 0x00000C42
#define CLK_SPI6_CSI 0x00000C43
#define CLK_SPI6_HSE 0x00000C44
#define CLK_SPI6_PLL3Q 0x00000C45
#define CLK_SPI6_DISABLED 0x00000C47
#define CLK_UART6_PCLK2 0x00008E40
#define CLK_UART6_PLL4Q 0x00008E41
#define CLK_UART6_HSI 0x00008E42
#define CLK_UART6_CSI 0x00008E43
#define CLK_UART6_HSE 0x00008E44
#define CLK_UART6_DISABLED 0x00008E47
#define CLK_UART24_PCLK1 0x00008E80
#define CLK_UART24_PLL4Q 0x00008E81
#define CLK_UART24_HSI 0x00008E82
#define CLK_UART24_CSI 0x00008E83
#define CLK_UART24_HSE 0x00008E84
#define CLK_UART24_DISABLED 0x00008E87
#define CLK_UART35_PCLK1 0x00008EC0
#define CLK_UART35_PLL4Q 0x00008EC1
#define CLK_UART35_HSI 0x00008EC2
#define CLK_UART35_CSI 0x00008EC3
#define CLK_UART35_HSE 0x00008EC4
#define CLK_UART35_DISABLED 0x00008EC7
#define CLK_UART78_PCLK1 0x00008F00
#define CLK_UART78_PLL4Q 0x00008F01
#define CLK_UART78_HSI 0x00008F02
#define CLK_UART78_CSI 0x00008F03
#define CLK_UART78_HSE 0x00008F04
#define CLK_UART78_DISABLED 0x00008F07
#define CLK_UART1_PCLK5 0x00000C80
#define CLK_UART1_PLL3Q 0x00000C81
#define CLK_UART1_HSI 0x00000C82
#define CLK_UART1_CSI 0x00000C83
#define CLK_UART1_PLL4Q 0x00000C84
#define CLK_UART1_HSE 0x00000C85
#define CLK_UART1_DISABLED 0x00000C87
#define CLK_SDMMC12_HCLK6 0x00008F40
#define CLK_SDMMC12_PLL3R 0x00008F41
#define CLK_SDMMC12_PLL4P 0x00008F42
#define CLK_SDMMC12_HSI 0x00008F43
#define CLK_SDMMC12_DISABLED 0x00008F47
#define CLK_SDMMC3_HCLK2 0x00008F80
#define CLK_SDMMC3_PLL3R 0x00008F81
#define CLK_SDMMC3_PLL4P 0x00008F82
#define CLK_SDMMC3_HSI 0x00008F83
#define CLK_SDMMC3_DISABLED 0x00008F87
#define CLK_ETH_PLL4P 0x00008FC0
#define CLK_ETH_PLL3Q 0x00008FC1
#define CLK_ETH_DISABLED 0x00008FC3
#define CLK_QSPI_ACLK 0x00009000
#define CLK_QSPI_PLL3R 0x00009001
#define CLK_QSPI_PLL4P 0x00009002
#define CLK_QSPI_CKPER 0x00009003
#define CLK_FMC_ACLK 0x00009040
#define CLK_FMC_PLL3R 0x00009041
#define CLK_FMC_PLL4P 0x00009042
#define CLK_FMC_CKPER 0x00009043
#define CLK_FDCAN_HSE 0x000090C0
#define CLK_FDCAN_PLL3Q 0x000090C1
#define CLK_FDCAN_PLL4Q 0x000090C2
#define CLK_FDCAN_PLL4R 0x000090C3
#define CLK_SPDIF_PLL4P 0x00009140
#define CLK_SPDIF_PLL3Q 0x00009141
#define CLK_SPDIF_HSI 0x00009142
#define CLK_SPDIF_DISABLED 0x00009143
#define CLK_CEC_LSE 0x00009180
#define CLK_CEC_LSI 0x00009181
#define CLK_CEC_CSI_DIV122 0x00009182
#define CLK_CEC_DISABLED 0x00009183
#define CLK_USBPHY_HSE 0x000091C0
#define CLK_USBPHY_PLL4R 0x000091C1
#define CLK_USBPHY_HSE_DIV2 0x000091C2
#define CLK_USBPHY_DISABLED 0x000091C3
#define CLK_USBO_PLL4R 0x800091C0
#define CLK_USBO_USBPHY 0x800091C1
#define CLK_RNG1_CSI 0x00000CC0
#define CLK_RNG1_PLL4R 0x00000CC1
#define CLK_RNG1_LSE 0x00000CC2
#define CLK_RNG1_LSI 0x00000CC3
#define CLK_RNG2_CSI 0x00009200
#define CLK_RNG2_PLL4R 0x00009201
#define CLK_RNG2_LSE 0x00009202
#define CLK_RNG2_LSI 0x00009203
#define CLK_CKPER_HSI 0x00000D00
#define CLK_CKPER_CSI 0x00000D01
#define CLK_CKPER_HSE 0x00000D02
#define CLK_CKPER_DISABLED 0x00000D03
#define CLK_STGEN_HSI 0x00000D40
#define CLK_STGEN_HSE 0x00000D41
#define CLK_STGEN_DISABLED 0x00000D43
#define CLK_DSI_DSIPLL 0x00009240
#define CLK_DSI_PLL4P 0x00009241
#define CLK_ADC_PLL4R 0x00009280
#define CLK_ADC_CKPER 0x00009281
#define CLK_ADC_PLL3Q 0x00009282
#define CLK_ADC_DISABLED 0x00009283
#define CLK_LPTIM45_PCLK3 0x000092C0
#define CLK_LPTIM45_PLL4P 0x000092C1
#define CLK_LPTIM45_PLL3Q 0x000092C2
#define CLK_LPTIM45_LSE 0x000092C3
#define CLK_LPTIM45_LSI 0x000092C4
#define CLK_LPTIM45_CKPER 0x000092C5
#define CLK_LPTIM45_DISABLED 0x000092C7
#define CLK_LPTIM23_PCLK3 0x00009300
#define CLK_LPTIM23_PLL4Q 0x00009301
#define CLK_LPTIM23_CKPER 0x00009302
#define CLK_LPTIM23_LSE 0x00009303
#define CLK_LPTIM23_LSI 0x00009304
#define CLK_LPTIM23_DISABLED 0x00009307
#define CLK_LPTIM1_PCLK1 0x00009340
#define CLK_LPTIM1_PLL4P 0x00009341
#define CLK_LPTIM1_PLL3Q 0x00009342
#define CLK_LPTIM1_LSE 0x00009343
#define CLK_LPTIM1_LSI 0x00009344
#define CLK_LPTIM1_CKPER 0x00009345
#define CLK_LPTIM1_DISABLED 0x00009347
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#endif

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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
* Copyright (C) 2020-2022, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
#define _DT_BINDINGS_STM32MP1_RESET_H_
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786
/* SCMI reset domain identifiers */
#define RST_SCMI0_SPI6 0
#define RST_SCMI0_I2C4 1
#define RST_SCMI0_I2C6 2
#define RST_SCMI0_USART1 3
#define RST_SCMI0_STGEN 4
#define RST_SCMI0_GPIOZ 5
#define RST_SCMI0_CRYP1 6
#define RST_SCMI0_HASH1 7
#define RST_SCMI0_RNG1 8
#define RST_SCMI0_MDMA 9
#define RST_SCMI0_MCU 10
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
#if STM32MP13
#include "stm32mp13-resets.h"
#endif
#if STM32MP15
#include "stm32mp15-resets.h"
#endif

96
include/dt-bindings/reset/stm32mp13-resets.h Normal file
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@ -0,0 +1,96 @@
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP13_RESET_H_
#define _DT_BINDINGS_STM32MP13_RESET_H_
#define TIM2_R 13568
#define TIM3_R 13569
#define TIM4_R 13570
#define TIM5_R 13571
#define TIM6_R 13572
#define TIM7_R 13573
#define LPTIM1_R 13577
#define SPI2_R 13579
#define SPI3_R 13580
#define USART3_R 13583
#define UART4_R 13584
#define UART5_R 13585
#define UART7_R 13586
#define UART8_R 13587
#define I2C1_R 13589
#define I2C2_R 13590
#define SPDIF_R 13594
#define TIM1_R 13632
#define TIM8_R 13633
#define SPI1_R 13640
#define USART6_R 13645
#define SAI1_R 13648
#define SAI2_R 13649
#define DFSDM_R 13652
#define FDCAN_R 13656
#define LPTIM2_R 13696
#define LPTIM3_R 13697
#define LPTIM4_R 13698
#define LPTIM5_R 13699
#define SYSCFG_R 13707
#define VREF_R 13709
#define DTS_R 13712
#define PMBCTRL_R 13713
#define LTDC_R 13760
#define DCMIPP_R 13761
#define DDRPERFM_R 13768
#define USBPHY_R 13776
#define STGEN_R 13844
#define USART1_R 13888
#define USART2_R 13889
#define SPI4_R 13890
#define SPI5_R 13891
#define I2C3_R 13892
#define I2C4_R 13893
#define I2C5_R 13894
#define TIM12_R 13895
#define TIM13_R 13896
#define TIM14_R 13897
#define TIM15_R 13898
#define TIM16_R 13899
#define TIM17_R 13900
#define DMA1_R 13952
#define DMA2_R 13953
#define DMAMUX1_R 13954
#define DMA3_R 13955
#define DMAMUX2_R 13956
#define ADC1_R 13957
#define ADC2_R 13958
#define USBO_R 13960
#define GPIOA_R 14080
#define GPIOB_R 14081
#define GPIOC_R 14082
#define GPIOD_R 14083
#define GPIOE_R 14084
#define GPIOF_R 14085
#define GPIOG_R 14086
#define GPIOH_R 14087
#define GPIOI_R 14088
#define TSC_R 14095
#define PKA_R 14146
#define SAES_R 14147
#define CRYP1_R 14148
#define HASH1_R 14149
#define RNG1_R 14150
#define AXIMC_R 14160
#define MDMA_R 14208
#define MCE_R 14209
#define ETH1MAC_R 14218
#define FMC_R 14220
#define QSPI_R 14222
#define SDMMC1_R 14224
#define SDMMC2_R 14225
#define CRC1_R 14228
#define USBH_R 14232
#define ETH2MAC_R 14238
#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */

123
include/dt-bindings/reset/stm32mp15-resets.h Normal file
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@ -0,0 +1,123 @@
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP15_RESET_H_
#define _DT_BINDINGS_STM32MP15_RESET_H_
#define MCU_HOLD_BOOT_R 2144
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786
/* SCMI reset domain identifiers */
#define RST_SCMI0_SPI6 0
#define RST_SCMI0_I2C4 1
#define RST_SCMI0_I2C6 2
#define RST_SCMI0_USART1 3
#define RST_SCMI0_STGEN 4
#define RST_SCMI0_GPIOZ 5
#define RST_SCMI0_CRYP1 6
#define RST_SCMI0_HASH1 7
#define RST_SCMI0_RNG1 8
#define RST_SCMI0_MDMA 9
#define RST_SCMI0_MCU 10
#define RST_SCMI0_MCU_HOLD_BOOT 11
#endif /* _DT_BINDINGS_STM32MP15_RESET_H_ */

35
include/dt-bindings/soc/stm32mp13-tzc400.h Normal file
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@ -0,0 +1,35 @@
/*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_STM32MP13_TZC400_H
#define _DT_BINDINGS_STM32MP13_TZC400_H
#include <drivers/arm/tzc_common.h>
#define STM32MP1_TZC_A7_ID U(0)
#define STM32MP1_TZC_LCD_ID U(3)
#define STM32MP1_TZC_MDMA_ID U(5)
#define STM32MP1_TZC_DMA_ID U(6)
#define STM32MP1_TZC_USB_HOST_ID U(7)
#define STM32MP1_TZC_USB_OTG_ID U(8)
#define STM32MP1_TZC_SDMMC_ID U(9)
#define STM32MP1_TZC_ETH_ID U(10)
#define STM32MP1_TZC_DCMIPP_ID U(11)
#define STM32MP1_TZC_DAP_ID U(15)
#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \
(TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DCMIPP_ID) | \
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID))
#endif /* _DT_BINDINGS_STM32MP13_TZC400_H */

20
plat/st/stm32mp1/bl2_plat_setup.c
View File

@ -47,7 +47,9 @@ static const char debug_msg[] = {
};
#endif
#if STM32MP15
static struct stm32mp_auth_ops stm32mp1_auth_ops;
#endif
static void print_reset_reason(void)
{
@ -82,6 +84,7 @@ static void print_reset_reason(void)
return;
}
#if STM32MP15
if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" System reset generated by MCU (MCSYSRST)\n");
@ -90,6 +93,7 @@ static void print_reset_reason(void)
}
return;
}
#endif
if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
INFO(" System reset generated by MPU (MPSYSRST)\n");
@ -116,10 +120,12 @@ static void print_reset_reason(void)
return;
}
#if STM32MP15
if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
INFO(" MPU Processor 1 Reset\n");
return;
}
#endif
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" Pad Reset from NRST\n");
@ -171,6 +177,7 @@ void bl2_platform_setup(void)
#endif /* STM32MP_USE_STM32IMAGE */
}
#if STM32MP15
static void update_monotonic_counter(void)
{
uint32_t version;
@ -204,6 +211,7 @@ static void update_monotonic_counter(void)
version);
}
}
#endif
void bl2_el3_plat_arch_setup(void)
{
@ -271,8 +279,10 @@ void bl2_el3_plat_arch_setup(void)
mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
}
#if STM32MP15
/* Disable MCKPROT */
mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
#endif
/*
* Set minimum reset pulse duration to 31ms for discrete power
@ -307,7 +317,7 @@ void bl2_el3_plat_arch_setup(void)
stm32_save_boot_interface(boot_context->boot_interface_selected,
boot_context->boot_interface_instance);
#if STM32MP_USB_PROGRAMMER
#if STM32MP_USB_PROGRAMMER && STM32MP15
/* Deconfigure all UART RX pins configured by ROM code */
stm32mp1_deconfigure_uart_pins();
#endif
@ -338,6 +348,10 @@ skip_console_init:
if (dt_pmic_status() > 0) {
initialize_pmic();
if (pmic_voltages_init() != 0) {
ERROR("PMIC voltages init failed\n");
panic();
}
print_pmic_info_and_debug();
}
@ -359,6 +373,7 @@ skip_console_init:
}
}
#if STM32MP15
if (stm32mp_is_auth_supported()) {
stm32mp1_auth_ops.check_key =
boot_context->bootrom_ecdsa_check_key;
@ -367,12 +382,15 @@ skip_console_init:
stm32mp_init_auth(&stm32mp1_auth_ops);
}
#endif
stm32mp1_arch_security_setup();
print_reset_reason();
#if STM32MP15
update_monotonic_counter();
#endif
stm32mp1_syscfg_enable_io_compensation_finish();

100
plat/st/stm32mp1/include/boot_api.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,12 +13,22 @@
/*
* Possible value of boot context field 'auth_status'
*/
#if STM32MP13
/* No authentication done */
#define BOOT_API_CTX_AUTH_NO 0x7CFDD351U
/* Authentication done and failed */
#define BOOT_API_CTX_AUTH_FAILED 0x51330884U
/* Authentication done and success */
#define BOOT_API_CTX_AUTH_SUCCESS 0x67E8CAE1U
#endif
#if STM32MP15
/* No authentication done */
#define BOOT_API_CTX_AUTH_NO 0x0U
/* Authentication done and failed */
#define BOOT_API_CTX_AUTH_FAILED 0x1U
/* Authentication done and succeeded */
#define BOOT_API_CTX_AUTH_SUCCESS 0x2U
#endif
/*
* Possible value of boot context field 'boot_interface_sel'
@ -70,11 +80,17 @@
#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U
#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U
/* Image Header related definitions */
/* Definition of header version */
#if STM32MP13
#define BOOT_API_HEADER_VERSION 0x00020000U
#endif
#if STM32MP15
#define BOOT_API_HEADER_VERSION 0x00010000U
#endif
/*
* Magic number used to detect header in memory
@ -93,6 +109,49 @@
#define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1
#define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2
/*
* Extension headers related definitions
*/
/* 'bootapi_image_header_t.extension_flag' used for authentication feature */
#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0)
/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */
#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1)
/* 'bootapi_image_header_t.extension_flag' used for padding header feature */
#define BOOT_API_PADDING_EXTENSION_BIT BIT(31)
/*
* mask of bits of field 'bootapi_image_header_t.extension_flag'
* used for extension headers
*/
#define BOOT_API_ALL_EXTENSIONS_MASK \
(BOOT_API_AUTHENTICATION_EXTENSION_BIT | \
BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \
BOOT_API_PADDING_EXTENSION_BIT)
/*
* Magic number of FSBL decryption extension header
* The value shall gives the four bytes 'S','T',0x00,0x01 in memory
*/
#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U
/*
* Magic number of PKH revocation extension header
* The value shall gives the four bytes 'S','T',0x00,0x02 in memory
*/
#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U
/* Max number of ECDSA public key hash in table */
#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U
/* ECDSA public key hash table size in bytes */
#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \
(BOOT_API_AUTHENTICATION_NB_PKH_MAX * \
BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES)
/*
* Magic number of padding extension header
* The value shall gives the four bytes 'S','T',0xFF,0xFF in memory
*/
#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U
/*
* Cores secure magic numbers
* Constant to be stored in bakcup register
@ -157,11 +216,20 @@ typedef struct {
*/
uint16_t boot_interface_selected;
uint16_t boot_interface_instance;
#if STM32MP13
uint32_t reserved1[12];
#endif
#if STM32MP15
uint32_t reserved1[13];
#endif
uint32_t otp_afmux_values[3];
uint32_t reserved[5];
uint32_t reserved[3];
#if STM32MP15
uint32_t reserved2[2];
#endif
uint32_t auth_status;
#if STM32MP15
/*
* Pointers to bootROM External Secure Services
* - ECDSA check key
@ -179,7 +247,7 @@ typedef struct {
uint8_t *signature,
uint32_t ecc_algo,
uint32_t *entry_in);
#endif
/*
* Information specific to an SD boot
* Updated each time an SD boot is at least attempted,
@ -227,10 +295,10 @@ typedef struct {
uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES];
/*
* Checksum of payload
* 32-bit sum all all payload bytes considered as 8 bit unigned numbers,
* discarding any overflow bits.
* 32-bit sum all payload bytes considered as 8 bit unsigned
* numbers, discarding any overflow bits.
* Use to check UART/USB downloaded image integrity when signature
* is not used (i.e bit 0 : 'No_sig_check' = 1 in option flags)
* is not used
*/
uint32_t payload_checksum;
/* Image header version : should have value BOOT_API_HEADER_VERSION */
@ -255,6 +323,25 @@ typedef struct {
* counter value in OTP_CFG4 prior executing the downloaded image
*/
uint32_t image_version;
#if STM32MP13
/*
* Extension flags :
*
* Bit 0 : Authentication extension header
* value 0 : No signature check request
* Bit 1 : Encryption extension header
* Bit 2 : Padding extension header
*/
uint32_t extension_flags;
/* Length in bytes of all extension headers */
uint32_t extension_headers_length;
/* Add binary type information */
uint32_t binary_type;
/* Pad up to 128 byte total size */
uint8_t pad[16];
#endif
#if STM32MP15
/*
* Option flags:
* Bit 0 : No signature check request : 'No_sig_check'
@ -280,6 +367,7 @@ typedef struct {
uint8_t pad[83];
/* Add binary type information */
uint8_t binary_type;
#endif
} __packed boot_api_image_header_t;
#endif /* BOOT_API_H */

10
plat/st/stm32mp1/include/stm32mp1_private.h
View File

@ -21,6 +21,16 @@ void stm32mp1_syscfg_init(void);
void stm32mp1_syscfg_enable_io_compensation_start(void);
void stm32mp1_syscfg_enable_io_compensation_finish(void);
void stm32mp1_syscfg_disable_io_compensation(void);
uint32_t stm32mp1_syscfg_get_chip_version(void);
uint32_t stm32mp1_syscfg_get_chip_dev_id(void);
#if STM32MP13
void stm32mp1_syscfg_boot_mode_enable(void);
void stm32mp1_syscfg_boot_mode_disable(void);
#endif
#if STM32MP15
static inline void stm32mp1_syscfg_boot_mode_enable(void){}
static inline void stm32mp1_syscfg_boot_mode_disable(void){}
#endif
void stm32mp1_deconfigure_uart_pins(void);

71
plat/st/stm32mp1/platform.mk
View File

@ -24,10 +24,52 @@ STM32_TF_VERSION ?= 0
# Enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC := 1
# Default Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
STM32MP13 ?= 0
STM32MP15 ?= 0
ifeq ($(STM32MP13),1)
ifeq ($(STM32MP15),1)
$(error Cannot enable both flags STM32MP13 and STM32MP15)
endif
STM32MP13 := 1
STM32MP15 := 0
else ifeq ($(STM32MP15),1)
STM32MP13 := 0
STM32MP15 := 1
else ifneq ($(findstring stm32mp13,$(DTB_FILE_NAME)),)
STM32MP13 := 1
STM32MP15 := 0
else ifneq ($(findstring stm32mp15,$(DTB_FILE_NAME)),)
STM32MP13 := 0
STM32MP15 := 1
endif
ifeq ($(STM32MP13),1)
# DDR controller with single AXI port and 16-bit interface
STM32MP_DDR_DUAL_AXI_PORT:= 0
STM32MP_DDR_32BIT_INTERFACE:= 0
# STM32 image header version v2.0
STM32_HEADER_VERSION_MAJOR:= 2
STM32_HEADER_VERSION_MINOR:= 0
endif
ifeq ($(STM32MP15),1)
# DDR controller with dual AXI port and 32-bit interface
STM32MP_DDR_DUAL_AXI_PORT:= 1
STM32MP_DDR_32BIT_INTERFACE:= 1
# STM32 image header version v1.0
STM32_HEADER_VERSION_MAJOR:= 1
STM32_HEADER_VERSION_MINOR:= 0
endif
# STM32 image header binary type for BL2
STM32_HEADER_BL2_BINARY_TYPE:= 0x10
ifeq ($(AARCH32_SP),sp_min)
# Disable Neon support: sp_min runtime may conflict with non-secure world
TF_CFLAGS += -mfloat-abi=soft
@ -82,7 +124,10 @@ STM32MP_USB_PROGRAMMER ?= 0
STM32MP_UART_PROGRAMMER ?= 0
# Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
ifeq ($(STM32MP13),1)
BL2_DTSI := stm32mp13-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
else
ifeq ($(STM32MP_USE_STM32IMAGE),1)
ifeq ($(AARCH32_SP),optee)
BL2_DTSI := stm32mp15-bl2.dtsi
@ -98,6 +143,7 @@ BL32_DTSI := stm32mp15-bl32.dtsi
FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME)))
endif
endif
endif
$(eval DTC_V = $(shell $(DTC) -v | awk '{print $$NF}'))
$(eval DTC_VERSION = $(shell printf "%d" $(shell echo ${DTC_V} | cut -d- -f1 | sed "s/\./0/g")))
@ -167,6 +213,8 @@ $(eval $(call assert_booleans,\
STM32MP_UART_PROGRAMMER \
STM32MP_USB_PROGRAMMER \
STM32MP_USE_STM32IMAGE \
STM32MP13 \
STM32MP15 \
)))
$(eval $(call assert_numerics,\
@ -196,6 +244,8 @@ $(eval $(call add_defines,\
STM32MP_UART_PROGRAMMER \
STM32MP_USB_PROGRAMMER \
STM32MP_USE_STM32IMAGE \
STM32MP13 \
STM32MP15 \
)))
# Include paths and source files
@ -230,7 +280,6 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/st/bsec/bsec2.c \
drivers/st/clk/stm32mp_clkfunc.c \
drivers/st/clk/stm32mp1_clk.c \
drivers/st/ddr/stm32mp_ddr.c \
drivers/st/ddr/stm32mp1_ddr_helpers.c \
drivers/st/gpio/stm32_gpio.c \
@ -246,6 +295,13 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
plat/st/stm32mp1/stm32mp1_helper.S \
plat/st/stm32mp1/stm32mp1_syscfg.c
ifeq ($(STM32MP13),1)
PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
drivers/st/clk/clk-stm32mp13.c
else
PLAT_BL_COMMON_SOURCES += drivers/st/clk/stm32mp1_clk.c
endif
ifneq (${STM32MP_USE_STM32IMAGE},1)
BL2_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES}
@ -275,9 +331,13 @@ BL2_SOURCES += drivers/io/io_block.c \
drivers/io/io_mtd.c \
drivers/io/io_storage.c \
drivers/st/crypto/stm32_hash.c \
plat/st/common/stm32mp_auth.c \
plat/st/stm32mp1/bl2_plat_setup.c
ifeq ($(STM32MP15),1)
BL2_SOURCES += plat/st/common/stm32mp_auth.c
endif
ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
BL2_SOURCES += drivers/mmc/mmc.c \
drivers/partition/gpt.c \
@ -427,5 +487,8 @@ tf-a-%.stm32: ${STM32IMAGE} tf-a-%.bin
$(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
${Q}${STM32IMAGE} -s $(word 2,$^) -d $@ \
-l $(LOADADDR) -e ${ENTRY} \
-v ${STM32_TF_VERSION}
-v ${STM32_TF_VERSION} \
-m ${STM32_HEADER_VERSION_MAJOR} \
-n ${STM32_HEADER_VERSION_MINOR} \
-b ${STM32_HEADER_BL2_BINARY_TYPE}
@echo

4
plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
View File

@ -4,6 +4,10 @@
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq ($(STM32MP13),1)
$(error "SP_min is not supported on STM32MP13 platform")
endif
SP_MIN_WITH_SECURE_FIQ := 1
ifneq ($(STM32MP_USE_STM32IMAGE),1)

144
plat/st/stm32mp1/stm32mp1_def.h
View File

@ -36,6 +36,23 @@
/*******************************************************************************
* CHIP ID
******************************************************************************/
#if STM32MP13
#define STM32MP1_CHIP_ID U(0x501)
#define STM32MP135C_PART_NB U(0x05010000)
#define STM32MP135A_PART_NB U(0x05010001)
#define STM32MP133C_PART_NB U(0x050100C0)
#define STM32MP133A_PART_NB U(0x050100C1)
#define STM32MP131C_PART_NB U(0x050106C8)
#define STM32MP131A_PART_NB U(0x050106C9)
#define STM32MP135F_PART_NB U(0x05010800)
#define STM32MP135D_PART_NB U(0x05010801)
#define STM32MP133F_PART_NB U(0x050108C0)
#define STM32MP133D_PART_NB U(0x050108C1)
#define STM32MP131F_PART_NB U(0x05010EC8)
#define STM32MP131D_PART_NB U(0x05010EC9)
#endif
#if STM32MP15
#define STM32MP1_CHIP_ID U(0x500)
#define STM32MP157C_PART_NB U(0x05000000)
@ -50,17 +67,25 @@
#define STM32MP153D_PART_NB U(0x050000A5)
#define STM32MP151F_PART_NB U(0x050000AE)
#define STM32MP151D_PART_NB U(0x050000AF)
#endif
#define STM32MP1_REV_B U(0x2000)
#if STM32MP13
#define STM32MP1_REV_Z U(0x1001)
#endif
#if STM32MP15
#define STM32MP1_REV_Z U(0x2001)
#endif
/*******************************************************************************
* PACKAGE ID
******************************************************************************/
#if STM32MP15
#define PKG_AA_LFBGA448 U(4)
#define PKG_AB_LFBGA354 U(3)
#define PKG_AC_TFBGA361 U(2)
#define PKG_AD_TFBGA257 U(1)
#endif
/*******************************************************************************
* STM32MP1 memory map related constants
@ -69,8 +94,22 @@
#define STM32MP_ROM_SIZE U(0x00020000)
#define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
#if STM32MP13
#define STM32MP_SYSRAM_BASE U(0x2FFE0000)
#define STM32MP_SYSRAM_SIZE U(0x00020000)
#define SRAM1_BASE U(0x30000000)
#define SRAM1_SIZE U(0x00004000)
#define SRAM2_BASE U(0x30004000)
#define SRAM2_SIZE U(0x00002000)
#define SRAM3_BASE U(0x30006000)
#define SRAM3_SIZE U(0x00002000)
#define SRAMS_BASE SRAM1_BASE
#define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
#endif /* STM32MP13 */
#if STM32MP15
#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
#define STM32MP_SYSRAM_SIZE U(0x00040000)
#endif /* STM32MP15 */
#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
@ -98,6 +137,15 @@ enum ddr_type {
#endif
/* Section used inside TF binaries */
#if STM32MP13
/* 512 Octets reserved for header */
#define STM32MP_HEADER_RESERVED_SIZE U(0x200)
#define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE
#define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE
#endif
#if STM32MP15
#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
/* 256 Octets reserved for header */
#define STM32MP_HEADER_SIZE U(0x00000100)
@ -111,6 +159,7 @@ enum ddr_type {
#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
(STM32MP_PARAM_LOAD_SIZE + \
STM32MP_HEADER_SIZE))
#endif
/* BL2 and BL32/sp_min require finer granularity tables */
#if defined(IMAGE_BL2)
@ -170,9 +219,11 @@ enum ddr_type {
#define GPIOG_BASE U(0x50008000)
#define GPIOH_BASE U(0x50009000)
#define GPIOI_BASE U(0x5000A000)
#if STM32MP15
#define GPIOJ_BASE U(0x5000B000)
#define GPIOK_BASE U(0x5000C000)
#define GPIOZ_BASE U(0x54004000)
#endif
#define GPIO_BANK_OFFSET U(0x1000)
/* Bank IDs used in GPIO driver API */
@ -185,11 +236,13 @@ enum ddr_type {
#define GPIO_BANK_G U(6)
#define GPIO_BANK_H U(7)
#define GPIO_BANK_I U(8)
#if STM32MP15
#define GPIO_BANK_J U(9)
#define GPIO_BANK_K U(10)
#define GPIO_BANK_Z U(25)
#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
#endif
/*******************************************************************************
* STM32MP1 UART
@ -205,6 +258,18 @@ enum ddr_type {
/* For UART crash console */
#define STM32MP_DEBUG_USART_BASE UART4_BASE
#if STM32MP13
/* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */
#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE
#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR
#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN
#define DEBUG_UART_TX_GPIO_PORT 6
#define DEBUG_UART_TX_GPIO_ALTERNATE 8
#define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR
#define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI
#endif /* STM32MP13 */
#if STM32MP15
/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
@ -214,6 +279,7 @@ enum ddr_type {
#define DEBUG_UART_TX_GPIO_ALTERNATE 6
#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
#endif /* STM32MP15 */
#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
@ -322,8 +388,13 @@ enum ddr_type {
******************************************************************************/
#define STM32MP1_TZC_BASE U(0x5C006000)
#if STM32MP13
#define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0)
#endif
#if STM32MP15
#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
TZC_400_REGION_ATTR_FILTER_BIT(1))
#endif
/*******************************************************************************
* STM32MP1 SDMMC
@ -349,7 +420,9 @@ enum ddr_type {
/* OTP labels */
#define CFG0_OTP "cfg0_otp"
#define PART_NUMBER_OTP "part_number_otp"
#if STM32MP15
#define PACKAGE_OTP "package_otp"
#endif
#define HW2_OTP "hw2_otp"
#define NAND_OTP "nand_otp"
#define MONOTONIC_OTP "monotonic_otp"
@ -358,15 +431,32 @@ enum ddr_type {
/* OTP mask */
/* CFG0 */
#if STM32MP13
#define CFG0_OTP_MODE_MASK GENMASK_32(9, 0)
#define CFG0_OTP_MODE_SHIFT 0
#define CFG0_OPEN_DEVICE 0x17U
#define CFG0_CLOSED_DEVICE 0x3FU
#define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU
#define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU
#endif
#if STM32MP15
#define CFG0_CLOSED_DEVICE BIT(6)
#endif
/* PART NUMBER */
#if STM32MP13
#define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0)
#endif
#if STM32MP15
#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
#endif
#define PART_NUMBER_OTP_PART_SHIFT 0
/* PACKAGE */
#if STM32MP15
#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
#define PACKAGE_OTP_PKG_SHIFT 27
#endif
/* IWDG OTP */
#define HW2_OTP_IWDG_HW_POS U(3)
@ -463,34 +553,84 @@ static inline uintptr_t tamp_bkpr(uint32_t idx)
* Miscellaneous STM32MP1 peripherals base address
******************************************************************************/
#define BSEC_BASE U(0x5C005000)
#if STM32MP13
#define CRYP_BASE U(0x54002000)
#endif
#if STM32MP15
#define CRYP1_BASE U(0x54001000)
#endif
#define DBGMCU_BASE U(0x50081000)
#if STM32MP13
#define HASH_BASE U(0x54003000)
#endif
#if STM32MP15
#define HASH1_BASE U(0x54002000)
#endif
#if STM32MP13
#define I2C3_BASE U(0x4C004000)
#define I2C4_BASE U(0x4C005000)
#define I2C5_BASE U(0x4C006000)
#endif
#if STM32MP15
#define I2C4_BASE U(0x5C002000)
#define I2C6_BASE U(0x5c009000)
#endif
#if STM32MP13
#define RNG_BASE U(0x54004000)
#endif
#if STM32MP15
#define RNG1_BASE U(0x54003000)
#endif
#define RTC_BASE U(0x5c004000)
#if STM32MP13
#define SPI4_BASE U(0x4C002000)
#define SPI5_BASE U(0x4C003000)
#endif
#if STM32MP15
#define SPI6_BASE U(0x5c001000)
#endif
#define STGEN_BASE U(0x5c008000)
#define SYSCFG_BASE U(0x50020000)
/*******************************************************************************
* STM32MP13 SAES
******************************************************************************/
#define SAES_BASE U(0x54005000)
/*******************************************************************************
* STM32MP13 PKA
******************************************************************************/
#define PKA_BASE U(0x54006000)
/*******************************************************************************
* REGULATORS
******************************************************************************/
/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
#define PLAT_NB_RDEVS U(19)
/* 1 FIXED */
#define PLAT_NB_FIXED_REGS U(1)
/* 2 FIXED */
#define PLAT_NB_FIXED_REGS U(2)
/*******************************************************************************
* Device Tree defines
******************************************************************************/
#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
#if STM32MP13
#define DT_DDR_COMPAT "st,stm32mp13-ddr"
#endif
#if STM32MP15
#define DT_DDR_COMPAT "st,stm32mp1-ddr"
#endif
#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
#define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout"
#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
#if STM32MP13
#define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc"
#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure"
#endif
#if STM32MP15
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
#endif
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
#endif /* STM32MP1_DEF_H */

7
plat/st/stm32mp1/stm32mp1_fconf_firewall.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -31,8 +31,13 @@ struct dt_id_attr {
void stm32mp1_arch_security_setup(void)
{
#if STM32MP13
clk_enable(TZC);
#endif
#if STM32MP15
clk_enable(TZC1);
clk_enable(TZC2);
#endif
tzc400_init(STM32MP1_TZC_BASE);
tzc400_disable_filters();

27
plat/st/stm32mp1/stm32mp1_fip_def.h
View File

@ -10,29 +10,51 @@
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
#if STM32MP13
#define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */
#define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */
#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */
#endif /* STM32MP13 */
#if STM32MP15
#define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */
#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */
#define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */
#endif /* STM32MP15 */
#define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */
#define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */
#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */
#if STM32MP13
#define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \
STM32MP_BL2_DTB_SIZE)
#endif /* STM32MP13 */
#if STM32MP15
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
#endif /* STM32MP15 */
#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
STM32MP_BL2_RO_SIZE)
#if STM32MP13
#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_RW_BASE)
#define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE
#endif /* STM32MP13 */
#if STM32MP15
#define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_RW_BASE)
#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_BL2_DTB_SIZE)
#endif /* STM32MP15 */
#define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE
@ -56,9 +78,14 @@
STM32MP_OPTEE_BASE)
#endif
#if STM32MP13
#define STM32MP_FW_CONFIG_BASE SRAM3_BASE
#endif /* STM32MP13 */
#if STM32MP15
#define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
PAGE_SIZE)
#endif /* STM32MP15 */
#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
STM32MP_BL33_MAX_SIZE)

130
plat/st/stm32mp1/stm32mp1_private.c
View File

@ -37,7 +37,12 @@
BOARD_ID_VARFG_SHIFT)
#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
#if STM32MP13
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(30)
#endif
#if STM32MP15
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(20)
#endif
#define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00)
#define TAMP_BOOT_MODE_ITF_SHIFT 8
@ -67,6 +72,15 @@
MT_EXECUTE_NEVER)
#endif
#if STM32MP13
#define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \
SRAMS_SIZE_2MB_ALIGNED, \
MT_MEMORY | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#endif
#define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
STM32MP1_DEVICE1_SIZE, \
MT_DEVICE | \
@ -84,6 +98,9 @@
#if defined(IMAGE_BL2)
static const mmap_region_t stm32mp1_mmap[] = {
MAP_SEC_SYSRAM,
#if STM32MP13
MAP_SRAM_ALL,
#endif
MAP_DEVICE1,
#if STM32MP_RAW_NAND
MAP_DEVICE2,
@ -111,42 +128,62 @@ void configure_mmu(void)
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
#if STM32MP13
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return GPIOZ_BASE;
}
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
#endif
return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
}
uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
{
#if STM32MP13
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return 0;
}
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
#endif
return bank * GPIO_BANK_OFFSET;
}
bool stm32_gpio_is_secure_at_reset(unsigned int bank)
{
#if STM32MP13
return true;
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return true;
}
return false;
#endif
}
unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
{
#if STM32MP13
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I);
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return GPIOZ;
}
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
#endif
return GPIOA + (bank - GPIO_BANK_A);
}
@ -163,11 +200,15 @@ int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank)
case GPIO_BANK_G:
case GPIO_BANK_H:
case GPIO_BANK_I:
#if STM32MP15
case GPIO_BANK_J:
case GPIO_BANK_K:
#endif
return fdt_path_offset(fdt, "/soc/pin-controller");
#if STM32MP15
case GPIO_BANK_Z:
return fdt_path_offset(fdt, "/soc/pin-controller-z");
#endif
default:
panic();
}
@ -248,6 +289,10 @@ void stm32mp1_deconfigure_uart_pins(void)
uint32_t stm32mp_get_chip_version(void)
{
#if STM32MP13
return stm32mp1_syscfg_get_chip_version();
#endif
#if STM32MP15
uint32_t version = 0U;
if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) {
@ -256,10 +301,15 @@ uint32_t stm32mp_get_chip_version(void)
}
return version;
#endif
}
uint32_t stm32mp_get_chip_dev_id(void)
{
#if STM32MP13
return stm32mp1_syscfg_get_chip_dev_id();
#endif
#if STM32MP15
uint32_t dev_id;
if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
@ -268,6 +318,7 @@ uint32_t stm32mp_get_chip_dev_id(void)
}
return dev_id;
#endif
}
static uint32_t get_part_number(void)
@ -290,6 +341,7 @@ static uint32_t get_part_number(void)
return part_number;
}
#if STM32MP15
static uint32_t get_cpu_package(void)
{
uint32_t package;
@ -303,6 +355,7 @@ static uint32_t get_cpu_package(void)
return package;
}
#endif
void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
{
@ -310,6 +363,45 @@ void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
/* MPUs Part Numbers */
switch (get_part_number()) {
#if STM32MP13
case STM32MP135F_PART_NB:
cpu_s = "135F";
break;
case STM32MP135D_PART_NB:
cpu_s = "135D";
break;
case STM32MP135C_PART_NB:
cpu_s = "135C";
break;
case STM32MP135A_PART_NB:
cpu_s = "135A";
break;
case STM32MP133F_PART_NB:
cpu_s = "133F";
break;
case STM32MP133D_PART_NB:
cpu_s = "133D";
break;
case STM32MP133C_PART_NB:
cpu_s = "133C";
break;
case STM32MP133A_PART_NB:
cpu_s = "133A";
break;
case STM32MP131F_PART_NB:
cpu_s = "131F";
break;
case STM32MP131D_PART_NB:
cpu_s = "131D";
break;
case STM32MP131C_PART_NB:
cpu_s = "131C";
break;
case STM32MP131A_PART_NB:
cpu_s = "131A";
break;
#endif
#if STM32MP15
case STM32MP157C_PART_NB:
cpu_s = "157C";
break;
@ -346,12 +438,18 @@ void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
case STM32MP151D_PART_NB:
cpu_s = "151D";
break;
#endif
default:
cpu_s = "????";
break;
}
/* Package */
#if STM32MP13
/* On STM32MP13, package is not present in OTP */
pkg = "";
#endif
#if STM32MP15
switch (get_cpu_package()) {
case PKG_AA_LFBGA448:
pkg = "AA";
@ -369,6 +467,7 @@ void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
pkg = "??";
break;
}
#endif
/* REVISION */
switch (stm32mp_get_chip_version()) {
@ -420,6 +519,10 @@ void stm32mp_print_boardinfo(void)
/* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
bool stm32mp_is_single_core(void)
{
#if STM32MP13
return true;
#endif
#if STM32MP15
bool single_core = false;
switch (get_part_number()) {
@ -434,6 +537,7 @@ bool stm32mp_is_single_core(void)
}
return single_core;
#endif
}
/* Return true when device is in closed state */
@ -445,7 +549,23 @@ bool stm32mp_is_closed_device(void)
return true;
}
#if STM32MP13
value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT;
switch (value) {
case CFG0_OPEN_DEVICE:
return false;
case CFG0_CLOSED_DEVICE:
case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN:
case CFG0_CLOSED_DEVICE_NO_JTAG:
return true;
default:
panic();
}
#endif
#if STM32MP15
return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE;
#endif
}
/* Return true when device supports secure boot */
@ -454,12 +574,22 @@ bool stm32mp_is_auth_supported(void)
bool supported = false;
switch (get_part_number()) {
#if STM32MP13
case STM32MP131C_PART_NB:
case STM32MP131F_PART_NB:
case STM32MP133C_PART_NB:
case STM32MP133F_PART_NB:
case STM32MP135C_PART_NB:
case STM32MP135F_PART_NB:
#endif
#if STM32MP15
case STM32MP151C_PART_NB:
case STM32MP151F_PART_NB:
case STM32MP153C_PART_NB:
case STM32MP153F_PART_NB:
case STM32MP157C_PART_NB:
case STM32MP157F_PART_NB:
#endif
supported = true;
break;
default:

193
plat/st/stm32mp1/stm32mp1_syscfg.c
View File

@ -4,11 +4,16 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <common/debug.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stpmic1.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <libfdt.h>
#include <platform_def.h>
#include <stm32mp_common.h>
@ -19,11 +24,24 @@
* SYSCFG REGISTER OFFSET (base relative)
*/
#define SYSCFG_BOOTR 0x00U
#define SYSCFG_BOOTCR 0x0CU
#if STM32MP15
#define SYSCFG_IOCTRLSETR 0x18U
#define SYSCFG_ICNR 0x1CU
#endif
#define SYSCFG_CMPCR 0x20U
#define SYSCFG_CMPENSETR 0x24U
#define SYSCFG_CMPENCLRR 0x28U
#if STM32MP13
#define SYSCFG_CMPSD1CR 0x30U
#define SYSCFG_CMPSD1ENSETR 0x34U
#define SYSCFG_CMPSD1ENCLRR 0x38U
#define SYSCFG_CMPSD2CR 0x40U
#define SYSCFG_CMPSD2ENSETR 0x44U
#define SYSCFG_CMPSD2ENCLRR 0x48U
#define SYSCFG_HSLVEN0R 0x50U
#endif
#define SYSCFG_IDC 0x380U
#define CMPCR_CMPENSETR_OFFSET 0x4U
#define CMPCR_CMPENCLRR_OFFSET 0x8U
@ -32,8 +50,16 @@
* SYSCFG_BOOTR Register
*/
#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
#if STM32MP15
#define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4)
#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
#endif
/*
* SYSCFG_BOOTCR Register
*/
#define SYSCFG_BOOTCR_BMEN BIT(0)
/*
* SYSCFG_IOCTRLSETR Register
*/
@ -65,6 +91,32 @@
*/
#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
/*
* HSLV definitions
*/
#define HSLV_IDX_TPIU 0U
#define HSLV_IDX_QSPI 1U
#define HSLV_IDX_ETH1 2U
#define HSLV_IDX_ETH2 3U
#define HSLV_IDX_SDMMC1 4U
#define HSLV_IDX_SDMMC2 5U
#define HSLV_IDX_SPI1 6U
#define HSLV_IDX_SPI2 7U
#define HSLV_IDX_SPI3 8U
#define HSLV_IDX_SPI4 9U
#define HSLV_IDX_SPI5 10U
#define HSLV_IDX_LTDC 11U
#define HSLV_NB_IDX 12U
#define HSLV_KEY 0x1018U
/*
* SYSCFG_IDC Register
*/
#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
#define SYSCFG_IDC_REV_ID_SHIFT 16
static void enable_io_comp_cell_finish(uintptr_t cmpcr_off)
{
uint64_t start;
@ -104,14 +156,107 @@ static void disable_io_comp_cell(uintptr_t cmpcr_off)
mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN);
}
#if STM32MP13
static int get_regu_max_voltage(void *fdt, int sdmmc_node,
const char *regu_name, uint32_t *regu_val)
{
int node;
const fdt32_t *cuint;
cuint = fdt_getprop(fdt, sdmmc_node, regu_name, NULL);
if (cuint == NULL) {
return -ENODEV;
}
node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
if (node < 0) {
return -ENODEV;
}
cuint = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL);
if (cuint == NULL) {
return -ENODEV;
}
*regu_val = fdt32_to_cpu(*cuint);
return 0;
}
static bool sdmmc_is_low_voltage(uintptr_t sdmmc_base)
{
int ret;
int node;
void *fdt = NULL;
uint32_t regu_max_val;
if (fdt_get_address(&fdt) == 0) {
return false;
}
if (fdt == NULL) {
return false;
}
node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, sdmmc_base);
if (node < 0) {
/* No SD or eMMC device on this instance, enable HSLV */
return true;
}
ret = get_regu_max_voltage(fdt, node, "vqmmc-supply", &regu_max_val);
if ((ret < 0) || (regu_max_val > 1800000U)) {
/*
* The vqmmc-supply property should always be present for eMMC.
* For SD-card, if it is not, then the card only supports 3.3V.
*/
return false;
}
return true;
}
static void enable_hslv_by_index(uint32_t index)
{
bool apply_hslv;
assert(index < HSLV_NB_IDX);
switch (index) {
case HSLV_IDX_SDMMC1:
apply_hslv = sdmmc_is_low_voltage(STM32MP_SDMMC1_BASE);
break;
case HSLV_IDX_SDMMC2:
apply_hslv = sdmmc_is_low_voltage(STM32MP_SDMMC2_BASE);
break;
default:
apply_hslv = true;
break;
}
if (apply_hslv) {
mmio_write_32(SYSCFG_BASE + SYSCFG_HSLVEN0R + index * sizeof(uint32_t), HSLV_KEY);
}
}
#endif
static void enable_high_speed_mode_low_voltage(void)
{
#if STM32MP13
uint32_t idx;
for (idx = 0U; idx < HSLV_NB_IDX; idx++) {
enable_hslv_by_index(idx);
}
#endif
#if STM32MP15
mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
SYSCFG_IOCTRLSETR_HSLVEN_ETH |
SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
SYSCFG_IOCTRLSETR_HSLVEN_SPI);
#endif
}
static void stm32mp1_syscfg_set_hslv(void)
@ -165,6 +310,7 @@ static void stm32mp1_syscfg_set_hslv(void)
void stm32mp1_syscfg_init(void)
{
#if STM32MP15
uint32_t bootr;
/*
@ -178,6 +324,7 @@ void stm32mp1_syscfg_init(void)
SYSCFG_BOOTR_BOOT_MASK;
mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
#endif
stm32mp1_syscfg_set_hslv();
@ -195,11 +342,22 @@ void stm32mp1_syscfg_enable_io_compensation_start(void)
mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR,
SYSCFG_CMPENSETR_MPU_EN);
#if STM32MP13
mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPSD1CR,
SYSCFG_CMPENSETR_MPU_EN);
mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPSD2CR,
SYSCFG_CMPENSETR_MPU_EN);
#endif
}
void stm32mp1_syscfg_enable_io_compensation_finish(void)
{
enable_io_comp_cell_finish(SYSCFG_CMPCR);
#if STM32MP13
enable_io_comp_cell_finish(SYSCFG_CMPSD1CR);
enable_io_comp_cell_finish(SYSCFG_CMPSD2CR);
#endif
}
void stm32mp1_syscfg_disable_io_compensation(void)
@ -213,6 +371,41 @@ void stm32mp1_syscfg_disable_io_compensation(void)
* Disable non-secure SYSCFG clock, we assume non-secure is suspended.
*/
disable_io_comp_cell(SYSCFG_CMPCR);
#if STM32MP13
disable_io_comp_cell(SYSCFG_CMPSD1CR);
disable_io_comp_cell(SYSCFG_CMPSD2CR);
#endif
clk_disable(SYSCFG);
}
/*
* @brief Get silicon revision from SYSCFG registers.
* @retval chip version (REV_ID).
*/
uint32_t stm32mp1_syscfg_get_chip_version(void)
{
return (mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) &
SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
}
/*
* @brief Get device ID from SYSCFG registers.
* @retval device ID (DEV_ID).
*/
uint32_t stm32mp1_syscfg_get_chip_dev_id(void)
{
return mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) & SYSCFG_IDC_DEV_ID_MASK;
}
#if STM32MP13
void stm32mp1_syscfg_boot_mode_enable(void)
{
mmio_setbits_32(SYSCFG_BASE + SYSCFG_BOOTCR, SYSCFG_BOOTCR_BMEN);
}
void stm32mp1_syscfg_boot_mode_disable(void)
{
mmio_clrbits_32(SYSCFG_BASE + SYSCFG_BOOTCR, SYSCFG_BOOTCR_BMEN);
}
#endif

34
plat/st/stm32mp1/stm32mp1_usb_dfu.c
View File

@ -28,7 +28,12 @@
#define USBD_CONFIGURATION_STRING "DFU Config"
#define USBD_INTERFACE_STRING "DFU Interface"
#if STM32MP13
#define USB_DFU_ITF_NUM 2
#endif
#if STM32MP15
#define USB_DFU_ITF_NUM 6
#endif
#define USB_DFU_CONFIG_DESC_SIZ USB_DFU_DESC_SIZ(USB_DFU_ITF_NUM)
@ -98,11 +103,18 @@ static const uint8_t usb_stm32mp1_config_desc[USB_DFU_CONFIG_DESC_SIZ] = {
/* Descriptor of DFU interface 0 Alternate setting 0..N */
USBD_DFU_IF_DESC(0),
USBD_DFU_IF_DESC(1),
#if USB_DFU_ITF_NUM > 2
USBD_DFU_IF_DESC(2),
#endif
#if USB_DFU_ITF_NUM > 3
USBD_DFU_IF_DESC(3),
#endif
#if USB_DFU_ITF_NUM > 4
USBD_DFU_IF_DESC(4),
#endif
#if USB_DFU_ITF_NUM > 5
USBD_DFU_IF_DESC(5),
#endif
/* DFU Functional Descriptor */
0x09, /* blength = 9 Bytes */
DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor */
@ -115,6 +127,13 @@ static const uint8_t usb_stm32mp1_config_desc[USB_DFU_CONFIG_DESC_SIZ] = {
};
/* The user strings: one by alternate as defined in USBD_DFU_IF_DESC */
#if STM32MP13
const char *const if_desc_string[USB_DFU_ITF_NUM] = {
"@SSBL /0x03/1*16Me",
"@virtual /0xF1/1*512Ba"
};
#endif
#if STM32MP15
const char *const if_desc_string[USB_DFU_ITF_NUM] = {
"@Partition0 /0x00/1*256Ke",
"@FSBL /0x01/1*1Me",
@ -123,6 +142,7 @@ const char *const if_desc_string[USB_DFU_ITF_NUM] = {
"@Partition4 /0x04/1*16Me",
"@virtual /0xF1/1*512Ba"
};
#endif
/* Buffer to build the unicode string provided to USB device stack */
static uint8_t usb_str_dec[USBD_MAX_STR_DESC_SIZ];
@ -354,9 +374,11 @@ struct usb_handle *usb_dfu_plat_init(void)
stm32mp1_usb_init_driver(&usb_core_handle, &pcd_handle,
(uint32_t *)USB_OTG_BASE);
#if STM32MP15
/* STM32MP15 = keep the configuration from ROM code */
usb_core_handle.ep0_state = USBD_EP0_DATA_IN;
usb_core_handle.dev_state = USBD_STATE_CONFIGURED;
#endif
/* Update the serial number string descriptor from the unique ID */
update_serial_num_string();
@ -376,12 +398,22 @@ uint8_t usb_dfu_get_phase(uint8_t alt)
uint8_t ret;
switch (alt) {
#if STM32MP13
case 0:
ret = PHASE_SSBL;
break;
case 1:
ret = PHASE_CMD;
break;
#endif
#if STM32MP15
case 3:
ret = PHASE_SSBL;
break;
case 5:
ret = PHASE_CMD;
break;
#endif
default:
ret = PHASE_RESET;
break;

194
tools/stm32image/stm32image.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,16 +22,16 @@
#define VER_MINOR 1
#define VER_VARIANT 0
#define HEADER_VERSION_V1 0x1
#define TF_BINARY_TYPE 0x10
#define HEADER_VERSION_V2 0x2
#define PADDING_HEADER_MAGIC __be32_to_cpu(0x5354FFFF)
#define PADDING_HEADER_FLAG (1 << 31)
#define PADDING_HEADER_LENGTH 0x180
/* Default option : bit0 => no signature */
#define HEADER_DEFAULT_OPTION (__cpu_to_le32(0x00000001))
struct stm32_header {
struct stm32_header_v1 {
uint32_t magic_number;
uint8_t image_signature[64];
uint32_t image_checksum;
uint8_t header_version[4];
uint8_t header_version[4];
uint32_t image_length;
uint32_t image_entry_point;
uint32_t reserved1;
@ -45,31 +45,50 @@ struct stm32_header {
uint8_t binary_type;
};
static void stm32image_default_header(struct stm32_header *ptr)
struct stm32_header_v2 {
uint32_t magic_number;
uint8_t image_signature[64];
uint32_t image_checksum;
uint8_t header_version[4];
uint32_t image_length;
uint32_t image_entry_point;
uint32_t reserved1;
uint32_t load_address;
uint32_t reserved2;
uint32_t version_number;
uint32_t extension_flags;
uint32_t extension_headers_length;
uint32_t binary_type;
uint8_t padding[16];
uint32_t extension_header_type;
uint32_t extension_header_length;
uint8_t extension_padding[376];
};
static void stm32image_default_header(void *ptr)
{
if (!ptr) {
struct stm32_header_v1 *header = (struct stm32_header_v1 *)ptr;
if (!header) {
return;
}
ptr->magic_number = HEADER_MAGIC;
ptr->option_flags = HEADER_DEFAULT_OPTION;
ptr->ecdsa_algorithm = __cpu_to_le32(1);
ptr->version_number = __cpu_to_le32(0);
ptr->binary_type = TF_BINARY_TYPE;
header->magic_number = HEADER_MAGIC;
header->version_number = __cpu_to_le32(0);
}
static uint32_t stm32image_checksum(void *start, uint32_t len)
static uint32_t stm32image_checksum(void *start, uint32_t len,
uint32_t header_size)
{
uint32_t csum = 0;
uint32_t hdr_len = sizeof(struct stm32_header);
uint8_t *p;
if (len < hdr_len) {
if (len < header_size) {
return 0;
}
p = (unsigned char *)start + hdr_len;
len -= hdr_len;
p = (unsigned char *)start + header_size;
len -= header_size;
while (len > 0) {
csum += *p;
@ -82,7 +101,8 @@ static uint32_t stm32image_checksum(void *start, uint32_t len)
static void stm32image_print_header(const void *ptr)
{
struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
struct stm32_header_v1 *stm32hdr = (struct stm32_header_v1 *)ptr;
struct stm32_header_v2 *stm32hdr_v2 = (struct stm32_header_v2 *)ptr;
printf("Image Type : ST Microelectronics STM32 V%d.%d\n",
stm32hdr->header_version[VER_MAJOR],
@ -95,40 +115,87 @@ static void stm32image_print_header(const void *ptr)
__le32_to_cpu(stm32hdr->image_entry_point));
printf("Checksum : 0x%08x\n",
__le32_to_cpu(stm32hdr->image_checksum));
printf("Option : 0x%08x\n",
__le32_to_cpu(stm32hdr->option_flags));
printf("Version : 0x%08x\n",
switch (stm32hdr->header_version[VER_MAJOR]) {
case HEADER_VERSION_V1:
printf("Option : 0x%08x\n",
__le32_to_cpu(stm32hdr->option_flags));
break;
case HEADER_VERSION_V2:
printf("Extension : 0x%08x\n",
__le32_to_cpu(stm32hdr_v2->extension_flags));
break;
default:
printf("Incorrect header version\n");
}
printf("Version : 0x%08x\n",
__le32_to_cpu(stm32hdr->version_number));
}
static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
uint32_t loadaddr, uint32_t ep, uint32_t ver,
uint32_t major, uint32_t minor)
static int stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
uint32_t loadaddr, uint32_t ep, uint32_t ver,
uint32_t major, uint32_t minor,
uint32_t binary_type, uint32_t header_size)
{
struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
struct stm32_header_v1 *stm32hdr = (struct stm32_header_v1 *)ptr;
struct stm32_header_v2 *stm32hdr_v2 = (struct stm32_header_v2 *)ptr;
uint32_t ext_size = 0U;
uint32_t ext_flags = 0U;
stm32image_default_header(stm32hdr);
stm32image_default_header(ptr);
stm32hdr->header_version[VER_MAJOR] = major;
stm32hdr->header_version[VER_MINOR] = minor;
stm32hdr->load_address = __cpu_to_le32(loadaddr);
stm32hdr->image_entry_point = __cpu_to_le32(ep);
stm32hdr->image_length = __cpu_to_le32((uint32_t)sbuf->st_size -
sizeof(struct stm32_header));
header_size);
stm32hdr->image_checksum =
__cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size));
__cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size,
header_size));
switch (stm32hdr->header_version[VER_MAJOR]) {
case HEADER_VERSION_V1:
/* Default option for header v1 : bit0 => no signature */
stm32hdr->option_flags = __cpu_to_le32(0x00000001);
stm32hdr->ecdsa_algorithm = __cpu_to_le32(1);
stm32hdr->binary_type = (uint8_t)binary_type;
break;
case HEADER_VERSION_V2:
stm32hdr_v2->binary_type = binary_type;
ext_size += PADDING_HEADER_LENGTH;
ext_flags |= PADDING_HEADER_FLAG;
stm32hdr_v2->extension_flags =
__cpu_to_le32(ext_flags);
stm32hdr_v2->extension_headers_length =
__cpu_to_le32(ext_size);
stm32hdr_v2->extension_header_type = PADDING_HEADER_MAGIC;
stm32hdr_v2->extension_header_length =
__cpu_to_le32(PADDING_HEADER_LENGTH);
break;
default:
return -1;
}
stm32hdr->version_number = __cpu_to_le32(ver);
return 0;
}
static int stm32image_create_header_file(char *srcname, char *destname,
uint32_t loadaddr, uint32_t entry,
uint32_t version, uint32_t major,
uint32_t minor)
uint32_t minor, uint32_t binary_type)
{
int src_fd, dest_fd;
int src_fd, dest_fd, header_size;
struct stat sbuf;
unsigned char *ptr;
struct stm32_header stm32image_header;
void *stm32image_header;
dest_fd = open(destname, O_RDWR | O_CREAT | O_TRUNC | O_APPEND, 0666);
if (dest_fd == -1) {
@ -154,15 +221,32 @@ static int stm32image_create_header_file(char *srcname, char *destname,
return -1;
}
memset(&stm32image_header, 0, sizeof(struct stm32_header));
switch (major) {
case HEADER_VERSION_V1:
stm32image_header = malloc(sizeof(struct stm32_header_v1));
header_size = sizeof(struct stm32_header_v1);
break;
if (write(dest_fd, &stm32image_header, sizeof(struct stm32_header)) !=
sizeof(struct stm32_header)) {
fprintf(stderr, "Write error %s: %s\n", destname,
strerror(errno));
case HEADER_VERSION_V2:
stm32image_header = malloc(sizeof(struct stm32_header_v2));
header_size = sizeof(struct stm32_header_v2);
break;
default:
return -1;
}
memset(stm32image_header, 0, header_size);
if (write(dest_fd, stm32image_header, header_size) !=
header_size) {
fprintf(stderr, "Write error %s: %s\n", destname,
strerror(errno));
free(stm32image_header);
return -1;
}
free(stm32image_header);
if (write(dest_fd, ptr, sbuf.st_size) != sbuf.st_size) {
fprintf(stderr, "Write error on %s: %s\n", destname,
strerror(errno));
@ -184,8 +268,11 @@ static int stm32image_create_header_file(char *srcname, char *destname,
return -1;
}
stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, entry, version,
major, minor);
if (stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr,
entry, version, major, minor,
binary_type, header_size) != 0) {
return -1;
}
stm32image_print_header(ptr);
@ -196,13 +283,22 @@ static int stm32image_create_header_file(char *srcname, char *destname,
int main(int argc, char *argv[])
{
int opt, loadaddr = -1, entry = -1, err = 0, version = 0;
int major = HEADER_VERSION_V1;
int opt;
int loadaddr = -1;
int entry = -1;
int err = 0;
int version = 0;
int binary_type = -1;
int major = HEADER_VERSION_V2;
int minor = 0;
char *dest = NULL, *src = NULL;
char *dest = NULL;
char *src = NULL;
while ((opt = getopt(argc, argv, ":s:d:l:e:v:m:n:")) != -1) {
while ((opt = getopt(argc, argv, ":b:s:d:l:e:v:m:n:")) != -1) {
switch (opt) {
case 'b':
binary_type = strtol(optarg, NULL, 0);
break;
case 's':
src = optarg;
break;
@ -226,7 +322,7 @@ int main(int argc, char *argv[])
break;
default:
fprintf(stderr,
"Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point] [-m major] [-n minor]\n",
"Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point] [-m major] [-n minor] [-b binary_type]\n",
argv[0]);
return -1;
}
@ -252,8 +348,14 @@ int main(int argc, char *argv[])
return -1;
}
if (binary_type == -1) {
fprintf(stderr, "Missing -b option\n");
return -1;
}
err = stm32image_create_header_file(src, dest, loadaddr,
entry, version, major, minor);
entry, version, major, minor,
binary_type);
return err;
}