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refactor(drivers/marvell/comphy-3700): unify Generation Settings register names 

Sometimes we call the constants GENx_SET_y, sometimes GENx_SETTINGS_y,
and sometimes GENx_SETTING_y.

Unify this into GENx_SETy.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3810fb52b2897fe6730ef6e58d434c47cfef14a9
This commit is contained in:
Marek Behún 2021-12-08 00:52:28 +01:00
parent b7b0575d12
commit 30264e9788
2 changed files with 8 additions and 8 deletions
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6
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -684,7 +684,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
/*
* 6. Set G2 Spread Spectrum Clock Amplitude at 4K
*/
usb3_reg_set(reg_base, COMPHY_GEN2_SET_2,
usb3_reg_set(reg_base, COMPHY_GEN2_SET2,
G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK);
/*
@ -693,7 +693,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
*/
mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
RSVD_PH03FH_6_0_MASK;
usb3_reg_set(reg_base, COMPHY_GEN3_SET_2,
usb3_reg_set(reg_base, COMPHY_GEN3_SET2,
G3_VREG_RXTX_MAS_ISET_60U, mask);
/*
@ -769,7 +769,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
/*
* 15. Set capacitor value for FFE gain peaking to 0xF
*/
usb3_reg_set(reg_base, COMPHY_GEN2_SETTINGS_3,
usb3_reg_set(reg_base, COMPHY_GEN2_SET3,
COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK);
/*

10
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -96,16 +96,16 @@ enum {
#define ISOLATION_CTRL_ADDR(unit) (COMPHY_ISOLATION_REG * PHY_SHFT(unit))
#define PHY_ISOLATE_MODE BIT(15)
#define COMPHY_GEN2_SET_2 0x3e
#define GEN2_SETTING_2_ADDR(unit) (COMPHY_GEN2_SET_2 * PHY_SHFT(unit))
#define COMPHY_GEN2_SET2 0x3e
#define GEN2_SET2_ADDR(unit) (COMPHY_GEN2_SET2 * PHY_SHFT(unit))
#define G2_TX_SSC_AMP_VALUE_20 BIT(14)
#define G2_TX_SSC_AMP_OFF 9
#define G2_TX_SSC_AMP_LEN 7
#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
G2_TX_SSC_AMP_OFF)
#define COMPHY_GEN3_SET_2 0x3f
#define GEN3_SETTING_2_ADDR(unit) (COMPHY_GEN3_SET_2 * PHY_SHFT(unit))
#define COMPHY_GEN3_SET2 0x3f
#define GEN3_SET2_ADDR(unit) (COMPHY_GEN3_SET2 * PHY_SHFT(unit))
#define G3_TX_SSC_AMP_OFF 9
#define G3_TX_SSC_AMP_LEN 7
#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
@ -138,7 +138,7 @@ enum {
#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1 * PHY_SHFT(unit))
#define SEL_BITS_PCIE_FORCE BIT(15)
#define COMPHY_GEN2_SETTINGS_3 0x112
#define COMPHY_GEN2_SET3 0x112
#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF