Do not enable CCI on Foundation FVP
- The Foundation FVP only has one cluster and does not have CCI. Change-Id: If91e81ff72c52e448150089c4cfea3e4d6ae1232
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43ef4f1ee7
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@ -225,15 +225,6 @@ platform_cold_boot_init:; .type platform_cold_boot_init, %function
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bl dcivac
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bl dcivac
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str x19, [x1, x2]
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str x19, [x1, x2]
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/* ---------------------------------------------
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* Enable CCI-400 for this cluster. No need
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* for locks as no other cpu is active at the
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* moment
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* ---------------------------------------------
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*/
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mov x0, x19
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bl cci_enable_coherency
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/* ---------------------------------------------
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/* ---------------------------------------------
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* Architectural init. can be generic e.g.
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* Architectural init. can be generic e.g.
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* enabling stack alignment and platform spec-
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* enabling stack alignment and platform spec-
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@ -576,6 +576,7 @@ int platform_config_setup(void)
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platform_config[CONFIG_MAX_AFF1] = 1;
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platform_config[CONFIG_MAX_AFF1] = 1;
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platform_config[CONFIG_CPU_SETUP] = 0;
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platform_config[CONFIG_CPU_SETUP] = 0;
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platform_config[CONFIG_BASE_MMAP] = 0;
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platform_config[CONFIG_BASE_MMAP] = 0;
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platform_config[CONFIG_HAS_CCI] = 0;
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break;
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break;
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case HBI_FVP_BASE:
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case HBI_FVP_BASE:
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midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
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midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
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@ -587,6 +588,7 @@ int platform_config_setup(void)
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platform_config[CONFIG_MAX_AFF0] = 4;
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platform_config[CONFIG_MAX_AFF0] = 4;
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platform_config[CONFIG_MAX_AFF1] = 2;
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platform_config[CONFIG_MAX_AFF1] = 2;
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platform_config[CONFIG_BASE_MMAP] = 1;
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platform_config[CONFIG_BASE_MMAP] = 1;
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platform_config[CONFIG_HAS_CCI] = 1;
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break;
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break;
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default:
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default:
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assert(0);
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assert(0);
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@ -34,6 +34,7 @@
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#include <platform.h>
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#include <platform.h>
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#include <bl1.h>
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#include <bl1.h>
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#include <console.h>
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#include <console.h>
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#include <cci400.h>
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/*******************************************************************************
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* Declarations of linker defined symbols which will help us find the layout
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@ -126,6 +127,9 @@ void bl1_early_platform_setup(void)
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bl1_tzram_layout.free_size =
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bl1_tzram_layout.free_size =
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tzram_limit - bl1_coherent_ram_limit;
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tzram_limit - bl1_coherent_ram_limit;
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}
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}
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/* Initialize the platform config for future decision making */
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platform_config_setup();
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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@ -153,11 +157,23 @@ void bl1_platform_setup(void)
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/*******************************************************************************
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/*******************************************************************************
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* Perform the very early platform specific architecture setup here. At the
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* Perform the very early platform specific architecture setup here. At the
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* moment this is only intializes the mmu in a quick and dirty way. Later arch-
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* moment this only does basic initialization. Later architectural setup
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* itectural setup (bl1_arch_setup()) does not do anything platform specific.
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* (bl1_arch_setup()) does not do anything platform specific.
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******************************************************************************/
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******************************************************************************/
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void bl1_plat_arch_setup(void)
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void bl1_plat_arch_setup(void)
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{
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{
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unsigned long cci_setup;
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/*
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* Enable CCI-400 for this cluster. No need
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* for locks as no other cpu is active at the
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* moment
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*/
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_enable_coherency(read_mpidr());
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}
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configure_mmu(&bl1_tzram_layout,
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configure_mmu(&bl1_tzram_layout,
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TZROM_BASE, /* Read_only region start */
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TZROM_BASE, /* Read_only region start */
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TZROM_BASE + TZROM_SIZE, /* Read_only region size */
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TZROM_BASE + TZROM_SIZE, /* Read_only region size */
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@ -111,7 +111,7 @@ int fvp_affinst_off(unsigned long mpidr,
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{
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{
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int rc = PSCI_E_SUCCESS;
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int rc = PSCI_E_SUCCESS;
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unsigned int gicc_base, ectlr;
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unsigned int gicc_base, ectlr;
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unsigned long cpu_setup;
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unsigned long cpu_setup, cci_setup;
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switch (afflvl) {
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switch (afflvl) {
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case MPIDR_AFFLVL1:
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case MPIDR_AFFLVL1:
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@ -120,7 +120,10 @@ int fvp_affinst_off(unsigned long mpidr,
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* Disable coherency if this cluster is to be
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* Disable coherency if this cluster is to be
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* turned off
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* turned off
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*/
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*/
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_disable_coherency(mpidr);
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cci_disable_coherency(mpidr);
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}
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/*
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/*
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* Program the power controller to turn the
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* Program the power controller to turn the
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@ -187,7 +190,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
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{
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{
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int rc = PSCI_E_SUCCESS;
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int rc = PSCI_E_SUCCESS;
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unsigned int gicc_base, ectlr;
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unsigned int gicc_base, ectlr;
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unsigned long cpu_setup, linear_id;
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unsigned long cpu_setup, cci_setup, linear_id;
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mailbox *fvp_mboxes;
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mailbox *fvp_mboxes;
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/* Cannot allow NS world to execute trusted firmware code */
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/* Cannot allow NS world to execute trusted firmware code */
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@ -203,7 +206,10 @@ int fvp_affinst_suspend(unsigned long mpidr,
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* Disable coherency if this cluster is to be
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* Disable coherency if this cluster is to be
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* turned off
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* turned off
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*/
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*/
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_disable_coherency(mpidr);
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cci_disable_coherency(mpidr);
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}
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/*
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/*
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* Program the power controller to turn the
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* Program the power controller to turn the
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@ -270,7 +276,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
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unsigned int state)
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unsigned int state)
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{
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{
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int rc = PSCI_E_SUCCESS;
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int rc = PSCI_E_SUCCESS;
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unsigned long linear_id, cpu_setup;
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unsigned long linear_id, cpu_setup, cci_setup;
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mailbox *fvp_mboxes;
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mailbox *fvp_mboxes;
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unsigned int gicd_base, gicc_base, reg_val, ectlr;
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unsigned int gicd_base, gicc_base, reg_val, ectlr;
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@ -278,8 +284,12 @@ int fvp_affinst_on_finish(unsigned long mpidr,
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case MPIDR_AFFLVL1:
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case MPIDR_AFFLVL1:
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/* Enable coherency if this cluster was off */
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/* Enable coherency if this cluster was off */
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if (state == PSCI_STATE_OFF)
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if (state == PSCI_STATE_OFF) {
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_enable_coherency(mpidr);
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cci_enable_coherency(mpidr);
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}
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}
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break;
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break;
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case MPIDR_AFFLVL0:
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case MPIDR_AFFLVL0:
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@ -72,7 +72,9 @@
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/* Indicate whether the CPUECTLR SMP bit should be enabled. */
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/* Indicate whether the CPUECTLR SMP bit should be enabled. */
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#define CONFIG_CPU_SETUP 6
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#define CONFIG_CPU_SETUP 6
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#define CONFIG_BASE_MMAP 7
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#define CONFIG_BASE_MMAP 7
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#define CONFIG_LIMIT 8
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/* Indicates whether CCI should be enabled on the platform. */
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#define CONFIG_HAS_CCI 8
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#define CONFIG_LIMIT 9
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/*******************************************************************************
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/*******************************************************************************
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* Platform memory map related constants
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* Platform memory map related constants
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