allwinner: Add functions to control CPU power/reset
sun50i_cpu_on will be used by the PSCI implementation to initialize secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by PSCI directly, because it is not possible for a CPU to use this function to power itself down. Power cannot be shut off until the outputs are clamped, and MMIO does not work once the outputs are clamped. But at least CPU0 can shutdown the other cores early in the BL31 boot process and before shutting down the system. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Samuel Holland
Andre Przywara
parent
64b3d9d88e
commit
333d66cf4e
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@ -44,6 +44,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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/* Turn off all secondary CPUs */
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sunxi_disable_secondary_cpus(plat_my_core_pos());
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}
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void bl31_plat_arch_setup(void)
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@ -0,0 +1,85 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <sunxi_mmap.h>
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#include <sunxi_cpucfg.h>
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#include <utils_def.h>
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#include "sunxi_private.h"
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static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
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{
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
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return;
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INFO("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff);
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}
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static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
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{
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if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0)
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return;
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INFO("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
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/* Power enable sequence from original Allwinner sources */
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80);
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mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
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}
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void sunxi_cpu_off(unsigned int cluster, unsigned int core)
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{
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INFO("PSCI: Powering off cluster %d core %d\n", cluster, core);
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/* Deassert DBGPWRDUP */
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mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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/* Activate the core output clamps */
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mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Remove power from the CPU */
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sunxi_cpu_disable_power(cluster, core);
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}
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void sunxi_cpu_on(unsigned int cluster, unsigned int core)
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{
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INFO("PSCI: Powering on cluster %d core %d\n", cluster, core);
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/* Assert CPU core reset */
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mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
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/* Assert CPU power-on reset */
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mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Set CPU to start in AArch64 mode */
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mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core));
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/* Apply power to the CPU */
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sunxi_cpu_enable_power(cluster, core);
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/* Release the core output clamps */
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mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
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/* Deassert CPU power-on reset */
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mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
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/* Deassert CPU core reset */
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mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
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/* Assert DBGPWRDUP */
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mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
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}
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void sunxi_disable_secondary_cpus(unsigned int primary_cpu)
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{
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for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) {
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if (cpu == primary_cpu)
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continue;
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sunxi_cpu_off(cpu / PLATFORM_MAX_CPUS_PER_CLUSTER,
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cpu % PLATFORM_MAX_CPUS_PER_CLUSTER);
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}
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}
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@ -18,8 +18,13 @@
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#define SUNXI_WDOG0_CFG_REG (SUNXI_WDOG_BASE + 0x0014)
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#define SUNXI_WDOG0_MODE_REG (SUNXI_WDOG_BASE + 0x0018)
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#include "sunxi_private.h"
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static void __dead2 sunxi_system_off(void)
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{
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/* Turn off all secondary CPUs */
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sunxi_disable_secondary_cpus(plat_my_core_pos());
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ERROR("PSCI: Full shutdown not implemented, halting\n");
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wfi();
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panic();
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@ -8,5 +8,8 @@
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#define __SUNXI_PRIVATE_H__
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void sunxi_configure_mmu_el3(int flags);
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void sunxi_cpu_off(unsigned int cluster, unsigned int core);
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void sunxi_cpu_on(unsigned int cluster, unsigned int core);
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void sunxi_disable_secondary_cpus(unsigned int primary_cpu);
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#endif /* __SUNXI_PRIVATE_H__ */
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SUNXI_CPUCFG_H__
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#define __SUNXI_CPUCFG_H__
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#include <sunxi_mmap.h>
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/* c = cluster, n = core */
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#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 16)
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#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0004 + (c) * 16)
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#define SUNXI_CPUCFG_CACHE_CFG_REG0 (SUNXI_CPUCFG_BASE + 0x0008)
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#define SUNXI_CPUCFG_CACHE_CFG_REG1 (SUNXI_CPUCFG_BASE + 0x000c)
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#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x0020)
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#define SUNXI_CPUCFG_GLB_CTRL_REG (SUNXI_CPUCFG_BASE + 0x0028)
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#define SUNXI_CPUCFG_CPU_STS_REG(c) (SUNXI_CPUCFG_BASE + 0x0030 + (c) * 4)
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#define SUNXI_CPUCFG_L2_STS_REG (SUNXI_CPUCFG_BASE + 0x003c)
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#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0080 + (c) * 4)
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#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8)
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#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8)
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#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \
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(c) * 16 + (n) * 4)
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#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_PRCM_BASE + 0x0100 + (c) * 4)
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#define SUNXI_R_CPUCFG_CPUS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0000)
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#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0030 + (c) * 4)
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#define SUNXI_R_CPUCFG_SYS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
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#define SUNXI_R_CPUCFG_SS_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01a0)
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#define SUNXI_R_CPUCFG_CPU_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a4)
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#define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8)
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#define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac)
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#endif /* __SUNXI_CPUCFG_H__ */
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@ -28,6 +28,7 @@ BL31_SOURCES += drivers/arm/gic/common/gic_common.c \
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plat/common/plat_gicv2.c \
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plat/common/plat_psci_common.c \
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${AW_PLAT}/common/sunxi_bl31_setup.c \
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${AW_PLAT}/common/sunxi_cpu_ops.c \
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${AW_PLAT}/common/sunxi_pm.c \
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${AW_PLAT}/common/sunxi_topology.c
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