Merge pull request #1000 from dp-arm/dp/aarch32-boot
juno/aarch32: Fix boot on Cortex A57 and A72
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commit
38fe380a9a
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -266,6 +266,16 @@ endfunc plat_get_my_entrypoint
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* to AArch32 mode is then requested by writing into RMR_EL3.
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*/
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func juno_reset_to_aarch32_state
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/*
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* Invalidate all caches before the warm reset to AArch32 state.
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* This is required on the Juno AArch32 boot flow because the L2
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* unified cache may contain code and data from when the processor
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* was still executing in AArch64 state. This code only runs on
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* the primary core, all other cores are powered down.
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*/
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mov x0, #DCISW
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bl dcsw_op_all
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emit_movw w0, BL32_BASE
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emit_movt w1, BL32_BASE
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/* opcode "bx r0" to branch using r0 in AArch32 mode */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -29,4 +29,28 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
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return err;
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}
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/*
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* We need to override some of the platform functions when booting SP_MIN
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* on Juno AArch32.
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*/
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static unsigned int scp_boot_config;
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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arm_bl2_early_platform_setup(mem_layout);
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/* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */
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VERBOSE("BL2: Saving SCP Boot config = 0x%x\n", scp_boot_config);
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scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR);
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}
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void bl2_platform_setup(void)
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{
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arm_bl2_platform_setup();
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mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config);
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VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config);
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}
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#endif /* JUNO_AARCH32_EL3_RUNTIME */
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