Merge pull request #1000 from dp-arm/dp/aarch32-boot

juno/aarch32: Fix boot on Cortex A57 and A72
This commit is contained in:
davidcunado-arm 2017-06-27 23:10:47 +01:00 committed by GitHub
commit 38fe380a9a
2 changed files with 36 additions and 2 deletions

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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -266,6 +266,16 @@ endfunc plat_get_my_entrypoint
* to AArch32 mode is then requested by writing into RMR_EL3.
*/
func juno_reset_to_aarch32_state
/*
* Invalidate all caches before the warm reset to AArch32 state.
* This is required on the Juno AArch32 boot flow because the L2
* unified cache may contain code and data from when the processor
* was still executing in AArch64 state. This code only runs on
* the primary core, all other cores are powered down.
*/
mov x0, #DCISW
bl dcsw_op_all
emit_movw w0, BL32_BASE
emit_movt w1, BL32_BASE
/* opcode "bx r0" to branch using r0 in AArch32 mode */

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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -29,4 +29,28 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
return err;
}
/*
* We need to override some of the platform functions when booting SP_MIN
* on Juno AArch32.
*/
static unsigned int scp_boot_config;
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
arm_bl2_early_platform_setup(mem_layout);
/* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */
VERBOSE("BL2: Saving SCP Boot config = 0x%x\n", scp_boot_config);
scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR);
}
void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config);
VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config);
}
#endif /* JUNO_AARCH32_EL3_RUNTIME */