mediatek: mt8183: add MTK SPM driver
Add MTK SPM driver for suspend/resume scenario. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I8207eea95914da9e63c62f3afc8329f3ccd9a22c
This commit is contained in:
kenny liang
parent
f9f84f44fb
commit
3c25ba4407
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@ -23,6 +23,7 @@
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#include <plat_private.h>
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#include <platform_def.h>
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#include <scu.h>
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#include <spm.h>
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#include <drivers/ti/uart/uart_16550.h>
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static entry_point_info_t bl32_ep_info;
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@ -146,6 +147,7 @@ void bl31_platform_setup(void)
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#if SPMC_MODE == 1
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spmc_init();
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#endif
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spm_boot_init();
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}
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/*******************************************************************************
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@ -7,6 +7,24 @@
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#include <pmic_wrap_init.h>
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#include <pmic.h>
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void bcpu_enable(uint32_t en)
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{
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pwrap_write(PMIC_VPROC11_OP_EN, 0x1);
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if (en)
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pwrap_write(PMIC_VPROC11_CON0, 1);
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else
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pwrap_write(PMIC_VPROC11_CON0, 0);
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}
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void bcpu_sram_enable(uint32_t en)
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{
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pwrap_write(PMIC_VSRAM_PROC11_OP_EN, 0x1);
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if (en)
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pwrap_write(PMIC_VSRAM_PROC11_CON0, 1);
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else
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pwrap_write(PMIC_VSRAM_PROC11_CON0, 0);
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}
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void wk_pmic_enable_sdn_delay(void)
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{
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uint32_t con;
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@ -10,7 +10,11 @@
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enum {
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PMIC_TMA_KEY = 0x03a8,
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PMIC_PWRHOLD = 0x0a08,
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PMIC_PSEQ_ELR11 = 0x0a62
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PMIC_PSEQ_ELR11 = 0x0a62,
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PMIC_VPROC11_CON0 = 0x1388,
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PMIC_VPROC11_OP_EN = 0x1390,
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PMIC_VSRAM_PROC11_CON0 = 0x1b46,
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PMIC_VSRAM_PROC11_OP_EN = 0x1b4e
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};
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enum {
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@ -18,6 +22,8 @@ enum {
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};
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/* external API */
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void bcpu_enable(uint32_t en);
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void bcpu_sram_enable(uint32_t en);
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void wk_pmic_enable_sdn_delay(void);
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void pmic_power_off(void);
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@ -0,0 +1,328 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/bakery_lock.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <spm.h>
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#include <spm_pmic_wrap.h>
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DEFINE_BAKERY_LOCK(spm_lock);
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const char *wakeup_src_str[32] = {
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[0] = "R12_PCM_TIMER",
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[1] = "R12_SSPM_WDT_EVENT_B",
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[2] = "R12_KP_IRQ_B",
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[3] = "R12_APWDT_EVENT_B",
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[4] = "R12_APXGPT1_EVENT_B",
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[5] = "R12_CONN2AP_SPM_WAKEUP_B",
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[6] = "R12_EINT_EVENT_B",
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[7] = "R12_CONN_WDT_IRQ_B",
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[8] = "R12_CCIF0_EVENT_B",
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[9] = "R12_LOWBATTERY_IRQ_B",
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[10] = "R12_SSPM_SPM_IRQ_B",
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[11] = "R12_SCP_SPM_IRQ_B",
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[12] = "R12_SCP_WDT_EVENT_B",
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[13] = "R12_PCM_WDT_WAKEUP_B",
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[14] = "R12_USB_CDSC_B ",
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[15] = "R12_USB_POWERDWN_B",
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[16] = "R12_SYS_TIMER_EVENT_B",
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[17] = "R12_EINT_EVENT_SECURE_B",
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[18] = "R12_CCIF1_EVENT_B",
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[19] = "R12_UART0_IRQ_B",
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[20] = "R12_AFE_IRQ_MCU_B",
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[21] = "R12_THERM_CTRL_EVENT_B",
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[22] = "R12_SYS_CIRQ_IRQ_B",
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[23] = "R12_MD2AP_PEER_EVENT_B",
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[24] = "R12_CSYSPWREQ_B",
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[25] = "R12_MD1_WDT_B ",
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[26] = "R12_CLDMA_EVENT_B",
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[27] = "R12_SEJ_WDT_GPT_B",
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[28] = "R12_ALL_SSPM_WAKEUP_B",
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[29] = "R12_CPU_IRQ_B",
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[30] = "R12_CPU_WFI_AND_B"
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};
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const char *spm_get_firmware_version(void)
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{
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return "DYNAMIC_SPM_FW_VERSION";
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}
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void spm_lock_init(void)
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{
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bakery_lock_init(&spm_lock);
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}
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void spm_lock_get(void)
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{
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bakery_lock_get(&spm_lock);
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}
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void spm_lock_release(void)
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{
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bakery_lock_release(&spm_lock);
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}
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void spm_set_bootaddr(unsigned long bootaddr)
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{
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/* initialize core4~7 boot entry address */
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mmio_write_32(SW2SPM_MAILBOX_3, bootaddr);
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}
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void spm_set_cpu_status(int cpu)
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{
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if (cpu >= 0 && cpu < 4) {
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mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204);
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mmio_write_32(ROOT_CORE_ADDR, 0x10006208 + (cpu * 0x4));
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} else if (cpu >= 4 && cpu < 8) {
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mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218);
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mmio_write_32(ROOT_CORE_ADDR, 0x1000621c + ((cpu - 4) * 0x4));
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} else {
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ERROR("%s: error cpu number %d\n", __func__, cpu);
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}
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}
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void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
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{
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mmio_write_32(SPM_AP_STANDBY_CON,
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((pwrctrl->wfi_op & 0x1) << 0) |
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((pwrctrl->mp0_cputop_idle_mask & 0x1) << 1) |
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((pwrctrl->mp1_cputop_idle_mask & 0x1) << 2) |
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((pwrctrl->mcusys_idle_mask & 0x1) << 4) |
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((pwrctrl->mm_mask_b & 0x3) << 16) |
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((pwrctrl->md_ddr_en_0_dbc_en & 0x1) << 18) |
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((pwrctrl->md_ddr_en_1_dbc_en & 0x1) << 19) |
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((pwrctrl->md_mask_b & 0x3) << 20) |
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((pwrctrl->sspm_mask_b & 0x1) << 22) |
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((pwrctrl->scp_mask_b & 0x1) << 23) |
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((pwrctrl->srcclkeni_mask_b & 0x1) << 24) |
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((pwrctrl->md_apsrc_1_sel & 0x1) << 25) |
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((pwrctrl->md_apsrc_0_sel & 0x1) << 26) |
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((pwrctrl->conn_ddr_en_dbc_en & 0x1) << 27) |
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((pwrctrl->conn_mask_b & 0x1) << 28) |
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((pwrctrl->conn_apsrc_sel & 0x1) << 29));
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mmio_write_32(SPM_SRC_REQ,
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((pwrctrl->spm_apsrc_req & 0x1) << 0) |
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((pwrctrl->spm_f26m_req & 0x1) << 1) |
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((pwrctrl->spm_infra_req & 0x1) << 3) |
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((pwrctrl->spm_vrf18_req & 0x1) << 4) |
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((pwrctrl->spm_ddren_req & 0x1) << 7) |
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((pwrctrl->spm_rsv_src_req & 0x7) << 8) |
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((pwrctrl->spm_ddren_2_req & 0x1) << 11) |
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((pwrctrl->cpu_md_dvfs_sop_force_on & 0x1) << 16));
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mmio_write_32(SPM_SRC_MASK,
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((pwrctrl->csyspwreq_mask & 0x1) << 0) |
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((pwrctrl->ccif0_md_event_mask_b & 0x1) << 1) |
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((pwrctrl->ccif0_ap_event_mask_b & 0x1) << 2) |
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((pwrctrl->ccif1_md_event_mask_b & 0x1) << 3) |
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((pwrctrl->ccif1_ap_event_mask_b & 0x1) << 4) |
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((pwrctrl->ccif2_md_event_mask_b & 0x1) << 5) |
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((pwrctrl->ccif2_ap_event_mask_b & 0x1) << 6) |
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((pwrctrl->ccif3_md_event_mask_b & 0x1) << 7) |
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((pwrctrl->ccif3_ap_event_mask_b & 0x1) << 8) |
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((pwrctrl->md_srcclkena_0_infra_mask_b & 0x1) << 9) |
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((pwrctrl->md_srcclkena_1_infra_mask_b & 0x1) << 10) |
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((pwrctrl->conn_srcclkena_infra_mask_b & 0x1) << 11) |
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((pwrctrl->ufs_infra_req_mask_b & 0x1) << 12) |
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((pwrctrl->srcclkeni_infra_mask_b & 0x1) << 13) |
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((pwrctrl->md_apsrc_req_0_infra_mask_b & 0x1) << 14) |
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((pwrctrl->md_apsrc_req_1_infra_mask_b & 0x1) << 15) |
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((pwrctrl->conn_apsrcreq_infra_mask_b & 0x1) << 16) |
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((pwrctrl->ufs_srcclkena_mask_b & 0x1) << 17) |
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((pwrctrl->md_vrf18_req_0_mask_b & 0x1) << 18) |
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((pwrctrl->md_vrf18_req_1_mask_b & 0x1) << 19) |
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((pwrctrl->ufs_vrf18_req_mask_b & 0x1) << 20) |
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((pwrctrl->gce_vrf18_req_mask_b & 0x1) << 21) |
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((pwrctrl->conn_infra_req_mask_b & 0x1) << 22) |
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((pwrctrl->gce_apsrc_req_mask_b & 0x1) << 23) |
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((pwrctrl->disp0_apsrc_req_mask_b & 0x1) << 24) |
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((pwrctrl->disp1_apsrc_req_mask_b & 0x1) << 25) |
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((pwrctrl->mfg_req_mask_b & 0x1) << 26) |
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((pwrctrl->vdec_req_mask_b & 0x1) << 27));
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mmio_write_32(SPM_SRC2_MASK,
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((pwrctrl->md_ddr_en_0_mask_b & 0x1) << 0) |
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((pwrctrl->md_ddr_en_1_mask_b & 0x1) << 1) |
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((pwrctrl->conn_ddr_en_mask_b & 0x1) << 2) |
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((pwrctrl->ddren_sspm_apsrc_req_mask_b & 0x1) << 3) |
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((pwrctrl->ddren_scp_apsrc_req_mask_b & 0x1) << 4) |
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((pwrctrl->disp0_ddren_mask_b & 0x1) << 5) |
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((pwrctrl->disp1_ddren_mask_b & 0x1) << 6) |
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((pwrctrl->gce_ddren_mask_b & 0x1) << 7) |
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((pwrctrl->ddren_emi_self_refresh_ch0_mask_b & 0x1)
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<< 8) |
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((pwrctrl->ddren_emi_self_refresh_ch1_mask_b & 0x1)
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<< 9));
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mmio_write_32(SPM_WAKEUP_EVENT_MASK,
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((pwrctrl->spm_wakeup_event_mask & 0xffffffff) << 0));
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mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
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((pwrctrl->spm_wakeup_event_ext_mask & 0xffffffff)
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<< 0));
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mmio_write_32(SPM_SRC3_MASK,
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((pwrctrl->md_ddr_en_2_0_mask_b & 0x1) << 0) |
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((pwrctrl->md_ddr_en_2_1_mask_b & 0x1) << 1) |
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((pwrctrl->conn_ddr_en_2_mask_b & 0x1) << 2) |
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((pwrctrl->ddren2_sspm_apsrc_req_mask_b & 0x1) << 3) |
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((pwrctrl->ddren2_scp_apsrc_req_mask_b & 0x1) << 4) |
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((pwrctrl->disp0_ddren2_mask_b & 0x1) << 5) |
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((pwrctrl->disp1_ddren2_mask_b & 0x1) << 6) |
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((pwrctrl->gce_ddren2_mask_b & 0x1) << 7) |
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((pwrctrl->ddren2_emi_self_refresh_ch0_mask_b & 0x1)
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<< 8) |
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((pwrctrl->ddren2_emi_self_refresh_ch1_mask_b & 0x1)
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<< 9));
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mmio_write_32(MP0_CPU0_WFI_EN,
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((pwrctrl->mp0_cpu0_wfi_en & 0x1) << 0));
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mmio_write_32(MP0_CPU1_WFI_EN,
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((pwrctrl->mp0_cpu1_wfi_en & 0x1) << 0));
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mmio_write_32(MP0_CPU2_WFI_EN,
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((pwrctrl->mp0_cpu2_wfi_en & 0x1) << 0));
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mmio_write_32(MP0_CPU3_WFI_EN,
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((pwrctrl->mp0_cpu3_wfi_en & 0x1) << 0));
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mmio_write_32(MP1_CPU0_WFI_EN,
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((pwrctrl->mp1_cpu0_wfi_en & 0x1) << 0));
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mmio_write_32(MP1_CPU1_WFI_EN,
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((pwrctrl->mp1_cpu1_wfi_en & 0x1) << 0));
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mmio_write_32(MP1_CPU2_WFI_EN,
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((pwrctrl->mp1_cpu2_wfi_en & 0x1) << 0));
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mmio_write_32(MP1_CPU3_WFI_EN,
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((pwrctrl->mp1_cpu3_wfi_en & 0x1) << 0));
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}
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void spm_disable_pcm_timer(void)
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{
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mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
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}
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void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
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{
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uint32_t val, mask, isr;
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val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
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mmio_write_32(PCM_TIMER_VAL, val);
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mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB);
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mask = pwrctrl->wake_src;
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if (pwrctrl->csyspwreq_mask)
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mask &= ~WAKE_SRC_R12_CSYSPWREQ_B;
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mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
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isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB;
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mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX);
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}
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void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
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{
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mmio_write_32(SPM_SW_FLAG, pwrctrl->pcm_flags);
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mmio_write_32(SPM_SW_RSV_2, pwrctrl->pcm_flags1);
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}
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void spm_set_pcm_wdt(int en)
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{
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if (en) {
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mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB,
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SPM_REGWR_CFG_KEY);
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if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX)
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mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
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mmio_write_32(PCM_WDT_VAL,
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mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
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mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB);
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} else {
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mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB,
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SPM_REGWR_CFG_KEY);
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}
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}
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void spm_send_cpu_wakeup_event(void)
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{
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mmio_write_32(PCM_REG_DATA_INI, 0);
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mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
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}
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void spm_get_wakeup_status(struct wake_status *wakesta)
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{
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wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI);
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wakesta->r12 = mmio_read_32(SPM_SW_RSV_0);
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wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA);
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wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
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wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
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wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR);
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wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR);
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wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
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wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
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wakesta->req_sta = mmio_read_32(SRC_REQ_STA);
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wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG);
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wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2);
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wakesta->r15 = mmio_read_32(PCM_REG15_DATA);
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wakesta->debug_flag = mmio_read_32(SPM_SW_DEBUG);
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wakesta->debug_flag1 = mmio_read_32(WDT_LATCH_SPARE0_FIX);
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wakesta->event_reg = mmio_read_32(SPM_BSI_D2_SR);
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wakesta->isr = mmio_read_32(SPM_IRQ_STA);
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}
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void spm_clean_after_wakeup(void)
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{
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mmio_write_32(SPM_SW_RSV_0,
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mmio_read_32(SPM_WAKEUP_STA) |
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mmio_read_32(SPM_SW_RSV_0));
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mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
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mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~0);
|
||||
mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
|
||||
mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
|
||||
mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
|
||||
}
|
||||
|
||||
void spm_output_wake_reason(struct wake_status *wakesta, const char *scenario)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
if (wakesta->assert_pc != 0) {
|
||||
INFO("%s: PCM ASSERT AT %u, ULPOSC_CON = 0x%x\n",
|
||||
scenario, wakesta->assert_pc, mmio_read_32(ULPOSC_CON));
|
||||
goto spm_debug_flags;
|
||||
}
|
||||
|
||||
for (i = 0; i <= 31; i++) {
|
||||
if (wakesta->r12 & (1U << i)) {
|
||||
INFO("%s: wake up by %s, timer_out = %u\n",
|
||||
scenario, wakeup_src_str[i], wakesta->timer_out);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
spm_debug_flags:
|
||||
INFO("r15 = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
|
||||
wakesta->r15, wakesta->r13, wakesta->debug_flag,
|
||||
wakesta->debug_flag1);
|
||||
INFO("sw_flag = 0x%x 0x%x, r12 = 0x%x, r12_ext = 0x%x\n",
|
||||
wakesta->sw_flag, wakesta->sw_flag1, wakesta->r12,
|
||||
wakesta->r12_ext);
|
||||
INFO("idle_sta = 0x%x, req_sta = 0x%x, event_reg = 0x%x\n",
|
||||
wakesta->idle_sta, wakesta->req_sta, wakesta->event_reg);
|
||||
INFO("isr = 0x%x, raw_sta = 0x%x, raw_ext_sta = 0x%x\n",
|
||||
wakesta->isr, wakesta->raw_sta, wakesta->raw_ext_sta);
|
||||
INFO("wake_misc = 0x%x\n", wakesta->wake_misc);
|
||||
}
|
||||
|
||||
void spm_boot_init(void)
|
||||
{
|
||||
NOTICE("%s() start\n", __func__);
|
||||
|
||||
spm_lock_init();
|
||||
mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
|
||||
|
||||
NOTICE("%s() end\n", __func__);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
#include <spm.h>
|
||||
#include <spm_pmic_wrap.h>
|
||||
#include <lib/libc/string.h>
|
||||
|
||||
#define SLEEP_REG_MD_SPM_DVFS_CMD20 (SLEEP_REG_MD_BASE + 0x010)
|
||||
#define SLEEP_REG_MD_SPM_DVFS_CMD21 (SLEEP_REG_MD_BASE + 0x014)
|
||||
#define SLEEP_REG_MD_SPM_DVFS_CMD22 (SLEEP_REG_MD_BASE + 0x018)
|
||||
#define SLEEP_REG_MD_SPM_DVFS_CMD23 (SLEEP_REG_MD_BASE + 0x01C)
|
||||
|
||||
/* PMIC_WRAP -> PMIC MT6358 */
|
||||
#define VCORE_BASE_UV 50000
|
||||
#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
|
||||
#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
|
||||
|
||||
#define DEFAULT_VOLT_VSRAM (100000)
|
||||
#define DEFAULT_VOLT_VCORE (100000)
|
||||
#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
|
||||
#define MAX_RETRY_COUNT (100)
|
||||
#define SPM_DATA_SHIFT (16)
|
||||
|
||||
#define BUCK_VCORE_ELR0 0x14AA
|
||||
#define BUCK_VPROC12_CON0 0x1408
|
||||
#define BUCK_VPROC11_CON0 0x1388
|
||||
#define TOP_SPI_CON0 0x044C
|
||||
#define LDO_VSRAM_PROC12_CON0 0x1B88
|
||||
#define LDO_VSRAM_PROC11_CON0 0x1B46
|
||||
#define BUCK_VMODEM_ELR0 0x15A6
|
||||
|
||||
struct pmic_wrap_cmd {
|
||||
unsigned long cmd_addr;
|
||||
unsigned long cmd_wdata;
|
||||
};
|
||||
|
||||
struct pmic_wrap_setting {
|
||||
enum pmic_wrap_phase_id phase;
|
||||
struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
|
||||
struct {
|
||||
struct {
|
||||
unsigned long cmd_addr;
|
||||
unsigned long cmd_wdata;
|
||||
} _[NR_PMIC_WRAP_CMD];
|
||||
const int nr_idx;
|
||||
} set[NR_PMIC_WRAP_PHASE];
|
||||
};
|
||||
|
||||
static struct pmic_wrap_setting pw = {
|
||||
.phase = NR_PMIC_WRAP_PHASE,
|
||||
.addr = {{0, 0} },
|
||||
.set[PMIC_WRAP_PHASE_ALLINONE] = {
|
||||
._[CMD_0] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(70000),},
|
||||
._[CMD_1] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(80000),},
|
||||
._[CMD_2] = {BUCK_VPROC12_CON0, 0x3,},
|
||||
._[CMD_3] = {BUCK_VPROC12_CON0, 0x1,},
|
||||
._[CMD_4] = {BUCK_VPROC11_CON0, 0x3,},
|
||||
._[CMD_5] = {BUCK_VPROC11_CON0, 0x1,},
|
||||
._[CMD_6] = {TOP_SPI_CON0, 0x1,},
|
||||
._[CMD_7] = {TOP_SPI_CON0, 0x0,},
|
||||
._[CMD_8] = {BUCK_VPROC12_CON0, 0x0,},
|
||||
._[CMD_9] = {BUCK_VPROC12_CON0, 0x1,},
|
||||
._[CMD_10] = {BUCK_VPROC11_CON0, 0x0,},
|
||||
._[CMD_11] = {BUCK_VPROC11_CON0, 0x1,},
|
||||
._[CMD_12] = {LDO_VSRAM_PROC12_CON0, 0x0,},
|
||||
._[CMD_13] = {LDO_VSRAM_PROC12_CON0, 0x1,},
|
||||
._[CMD_14] = {LDO_VSRAM_PROC11_CON0, 0x0,},
|
||||
._[CMD_15] = {LDO_VSRAM_PROC11_CON0, 0x1,},
|
||||
._[CMD_20] = {BUCK_VMODEM_ELR0, VOLT_TO_PMIC_VAL(55000),},
|
||||
._[CMD_21] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(60000),},
|
||||
._[CMD_22] = {LDO_VSRAM_PROC11_CON0, 0x3,},
|
||||
._[CMD_23] = {LDO_VSRAM_PROC11_CON0, 0x1,},
|
||||
.nr_idx = NR_IDX_ALL
|
||||
}
|
||||
};
|
||||
|
||||
void _mt_spm_pmic_table_init(void)
|
||||
{
|
||||
struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
|
||||
{(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
|
||||
{(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
|
||||
{(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
|
||||
{(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
|
||||
{(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
|
||||
{(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
|
||||
{(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
|
||||
{(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
|
||||
{(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
|
||||
{(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
|
||||
{(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
|
||||
{(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
|
||||
{(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
|
||||
{(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
|
||||
{(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
|
||||
{(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
|
||||
{(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20,
|
||||
(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20,},
|
||||
{(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21,
|
||||
(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21,},
|
||||
{(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22,
|
||||
(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22,},
|
||||
{(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23,
|
||||
(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23,}
|
||||
};
|
||||
|
||||
memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
|
||||
}
|
||||
|
||||
void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
|
||||
{
|
||||
uint32_t idx, addr, data;
|
||||
|
||||
if (phase >= NR_PMIC_WRAP_PHASE)
|
||||
return;
|
||||
|
||||
if (pw.phase == phase)
|
||||
return;
|
||||
|
||||
if (pw.addr[0].cmd_addr == 0)
|
||||
_mt_spm_pmic_table_init();
|
||||
|
||||
pw.phase = phase;
|
||||
|
||||
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY |
|
||||
BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB);
|
||||
for (idx = 0; idx < pw.set[phase].nr_idx; idx++) {
|
||||
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
|
||||
data = pw.set[phase]._[idx].cmd_wdata;
|
||||
mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
|
||||
}
|
||||
}
|
||||
|
||||
void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
|
||||
uint32_t cmd_wdata)
|
||||
{
|
||||
uint32_t addr;
|
||||
|
||||
if (phase >= NR_PMIC_WRAP_PHASE)
|
||||
return;
|
||||
|
||||
if (idx >= pw.set[phase].nr_idx)
|
||||
return;
|
||||
|
||||
pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
|
||||
|
||||
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY |
|
||||
BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB);
|
||||
if (pw.phase == phase) {
|
||||
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
|
||||
mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
|
||||
{
|
||||
if (phase >= NR_PMIC_WRAP_PHASE)
|
||||
return 0;
|
||||
|
||||
if (idx >= pw.set[phase].nr_idx)
|
||||
return 0;
|
||||
|
||||
return pw.set[phase]._[idx].cmd_wdata;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/****************************************************************
|
||||
* Auto generated by DE, please DO NOT modify this file directly.
|
||||
*****************************************************************/
|
||||
|
||||
#ifndef SPM_PMIC_WRAP__H
|
||||
#define SPM_PMIC_WRAP__H
|
||||
|
||||
enum pmic_wrap_phase_id {
|
||||
PMIC_WRAP_PHASE_ALLINONE,
|
||||
NR_PMIC_WRAP_PHASE
|
||||
};
|
||||
|
||||
/* IDX mapping */
|
||||
enum {
|
||||
CMD_0, /* 0x0 *//* PMIC_WRAP_PHASE_ALLINONE */
|
||||
CMD_1, /* 0x1 */
|
||||
CMD_2, /* 0x2 */
|
||||
CMD_3, /* 0x3 */
|
||||
CMD_4, /* 0x4 */
|
||||
CMD_5, /* 0x5 */
|
||||
CMD_6, /* 0x6 */
|
||||
CMD_7, /* 0x7 */
|
||||
CMD_8, /* 0x8 */
|
||||
CMD_9, /* 0x9 */
|
||||
CMD_10, /* 0xA */
|
||||
CMD_11, /* 0xB */
|
||||
CMD_12, /* 0xC */
|
||||
CMD_13, /* 0xD */
|
||||
CMD_14, /* 0xE */
|
||||
CMD_15, /* 0xF */
|
||||
CMD_20, /* 0x14 */
|
||||
CMD_21, /* 0x15 */
|
||||
CMD_22, /* 0x16 */
|
||||
CMD_23, /* 0x17 */
|
||||
NR_IDX_ALL
|
||||
};
|
||||
|
||||
/* APIs */
|
||||
void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
|
||||
void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
|
||||
uint32_t idx, uint32_t cmd_wdata);
|
||||
uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx);
|
||||
#endif /* SPM_PMIC_WRAP__H */
|
||||
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <mt_gic_v3.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
#include <pmic.h>
|
||||
#include <spm.h>
|
||||
#include <uart.h>
|
||||
|
||||
#define SPM_SYSCLK_SETTLE 99
|
||||
|
||||
#define WAKE_SRC_FOR_SUSPEND \
|
||||
(WAKE_SRC_R12_PCM_TIMER | \
|
||||
WAKE_SRC_R12_SSPM_WDT_EVENT_B | \
|
||||
WAKE_SRC_R12_KP_IRQ_B | \
|
||||
WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B | \
|
||||
WAKE_SRC_R12_EINT_EVENT_B | \
|
||||
WAKE_SRC_R12_CONN_WDT_IRQ_B | \
|
||||
WAKE_SRC_R12_CCIF0_EVENT_B | \
|
||||
WAKE_SRC_R12_SSPM_SPM_IRQ_B | \
|
||||
WAKE_SRC_R12_SCP_SPM_IRQ_B | \
|
||||
WAKE_SRC_R12_SCP_WDT_EVENT_B | \
|
||||
WAKE_SRC_R12_USB_CDSC_B | \
|
||||
WAKE_SRC_R12_USB_POWERDWN_B | \
|
||||
WAKE_SRC_R12_SYS_TIMER_EVENT_B | \
|
||||
WAKE_SRC_R12_EINT_EVENT_SECURE_B | \
|
||||
WAKE_SRC_R12_CCIF1_EVENT_B | \
|
||||
WAKE_SRC_R12_MD2AP_PEER_EVENT_B | \
|
||||
WAKE_SRC_R12_MD1_WDT_B | \
|
||||
WAKE_SRC_R12_CLDMA_EVENT_B | \
|
||||
WAKE_SRC_R12_SEJ_WDT_GPT_B)
|
||||
|
||||
#define SLP_PCM_FLAGS \
|
||||
(SPM_FLAG_DIS_VCORE_DVS | SPM_FLAG_DIS_VCORE_DFS | \
|
||||
SPM_FLAG_DIS_ATF_ABORT | SPM_FLAG_DISABLE_MMSYS_DVFS | \
|
||||
SPM_FLAG_DIS_INFRA_PDN | SPM_FLAG_SUSPEND_OPTION)
|
||||
|
||||
#define SLP_PCM_FLAGS1 \
|
||||
(SPM_FLAG1_DISABLE_MCDSR)
|
||||
|
||||
static const struct pwr_ctrl suspend_ctrl = {
|
||||
.wake_src = WAKE_SRC_FOR_SUSPEND,
|
||||
.pcm_flags = SLP_PCM_FLAGS,
|
||||
.pcm_flags1 = SLP_PCM_FLAGS1,
|
||||
|
||||
/* SPM_AP_STANDBY_CON */
|
||||
.wfi_op = 0x1,
|
||||
.mp0_cputop_idle_mask = 0,
|
||||
.mp1_cputop_idle_mask = 0,
|
||||
.mcusys_idle_mask = 0,
|
||||
.mm_mask_b = 0,
|
||||
.md_ddr_en_0_dbc_en = 0x1,
|
||||
.md_ddr_en_1_dbc_en = 0,
|
||||
.md_mask_b = 0x1,
|
||||
.sspm_mask_b = 0x1,
|
||||
.scp_mask_b = 0x1,
|
||||
.srcclkeni_mask_b = 0x1,
|
||||
.md_apsrc_1_sel = 0,
|
||||
.md_apsrc_0_sel = 0,
|
||||
.conn_ddr_en_dbc_en = 0x1,
|
||||
.conn_mask_b = 0x1,
|
||||
.conn_apsrc_sel = 0,
|
||||
|
||||
/* SPM_SRC_REQ */
|
||||
.spm_apsrc_req = 0,
|
||||
.spm_f26m_req = 0,
|
||||
.spm_infra_req = 0,
|
||||
.spm_vrf18_req = 0,
|
||||
.spm_ddren_req = 0,
|
||||
.spm_rsv_src_req = 0,
|
||||
.spm_ddren_2_req = 0,
|
||||
.cpu_md_dvfs_sop_force_on = 0,
|
||||
|
||||
/* SPM_SRC_MASK */
|
||||
.csyspwreq_mask = 0x1,
|
||||
.ccif0_md_event_mask_b = 0x1,
|
||||
.ccif0_ap_event_mask_b = 0x1,
|
||||
.ccif1_md_event_mask_b = 0x1,
|
||||
.ccif1_ap_event_mask_b = 0x1,
|
||||
.ccif2_md_event_mask_b = 0x1,
|
||||
.ccif2_ap_event_mask_b = 0x1,
|
||||
.ccif3_md_event_mask_b = 0x1,
|
||||
.ccif3_ap_event_mask_b = 0x1,
|
||||
.md_srcclkena_0_infra_mask_b = 0x1,
|
||||
.md_srcclkena_1_infra_mask_b = 0,
|
||||
.conn_srcclkena_infra_mask_b = 0,
|
||||
.ufs_infra_req_mask_b = 0,
|
||||
.srcclkeni_infra_mask_b = 0,
|
||||
.md_apsrc_req_0_infra_mask_b = 0x1,
|
||||
.md_apsrc_req_1_infra_mask_b = 0x1,
|
||||
.conn_apsrcreq_infra_mask_b = 0x1,
|
||||
.ufs_srcclkena_mask_b = 0,
|
||||
.md_vrf18_req_0_mask_b = 0,
|
||||
.md_vrf18_req_1_mask_b = 0,
|
||||
.ufs_vrf18_req_mask_b = 0,
|
||||
.gce_vrf18_req_mask_b = 0,
|
||||
.conn_infra_req_mask_b = 0x1,
|
||||
.gce_apsrc_req_mask_b = 0,
|
||||
.disp0_apsrc_req_mask_b = 0,
|
||||
.disp1_apsrc_req_mask_b = 0,
|
||||
.mfg_req_mask_b = 0,
|
||||
.vdec_req_mask_b = 0,
|
||||
|
||||
/* SPM_SRC2_MASK */
|
||||
.md_ddr_en_0_mask_b = 0x1,
|
||||
.md_ddr_en_1_mask_b = 0,
|
||||
.conn_ddr_en_mask_b = 0x1,
|
||||
.ddren_sspm_apsrc_req_mask_b = 0x1,
|
||||
.ddren_scp_apsrc_req_mask_b = 0x1,
|
||||
.disp0_ddren_mask_b = 0x1,
|
||||
.disp1_ddren_mask_b = 0x1,
|
||||
.gce_ddren_mask_b = 0x1,
|
||||
.ddren_emi_self_refresh_ch0_mask_b = 0,
|
||||
.ddren_emi_self_refresh_ch1_mask_b = 0,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_MASK */
|
||||
.spm_wakeup_event_mask = 0xF1782218,
|
||||
|
||||
/* SPM_WAKEUP_EVENT_EXT_MASK */
|
||||
.spm_wakeup_event_ext_mask = 0xFFFFFFFF,
|
||||
|
||||
/* SPM_SRC3_MASK */
|
||||
.md_ddr_en_2_0_mask_b = 0x1,
|
||||
.md_ddr_en_2_1_mask_b = 0,
|
||||
.conn_ddr_en_2_mask_b = 0x1,
|
||||
.ddren2_sspm_apsrc_req_mask_b = 0x1,
|
||||
.ddren2_scp_apsrc_req_mask_b = 0x1,
|
||||
.disp0_ddren2_mask_b = 0,
|
||||
.disp1_ddren2_mask_b = 0,
|
||||
.gce_ddren2_mask_b = 0,
|
||||
.ddren2_emi_self_refresh_ch0_mask_b = 0,
|
||||
.ddren2_emi_self_refresh_ch1_mask_b = 0,
|
||||
|
||||
.mp0_cpu0_wfi_en = 0x1,
|
||||
.mp0_cpu1_wfi_en = 0x1,
|
||||
.mp0_cpu2_wfi_en = 0x1,
|
||||
.mp0_cpu3_wfi_en = 0x1,
|
||||
|
||||
.mp1_cpu0_wfi_en = 0x1,
|
||||
.mp1_cpu1_wfi_en = 0x1,
|
||||
.mp1_cpu2_wfi_en = 0x1,
|
||||
.mp1_cpu3_wfi_en = 0x1
|
||||
};
|
||||
|
||||
static uint32_t spm_set_sysclk_settle(void)
|
||||
{
|
||||
mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE);
|
||||
return mmio_read_32(SPM_CLK_SETTLE);
|
||||
}
|
||||
|
||||
void go_to_sleep_before_wfi(void)
|
||||
{
|
||||
int cpu = MPIDR_AFFLVL0_VAL(read_mpidr());
|
||||
uint32_t settle;
|
||||
|
||||
settle = spm_set_sysclk_settle();
|
||||
spm_set_cpu_status(cpu);
|
||||
spm_set_power_control(&suspend_ctrl);
|
||||
spm_set_wakeup_event(&suspend_ctrl);
|
||||
spm_set_pcm_flags(&suspend_ctrl);
|
||||
spm_send_cpu_wakeup_event();
|
||||
spm_set_pcm_wdt(0);
|
||||
spm_disable_pcm_timer();
|
||||
|
||||
if (is_infra_pdn(suspend_ctrl.pcm_flags))
|
||||
mt_uart_save();
|
||||
|
||||
if (!mt_console_uart_cg_status())
|
||||
console_switch_state(CONSOLE_FLAG_BOOT);
|
||||
|
||||
INFO("cpu%d: \"%s\", wakesrc = 0x%x, pcm_con1 = 0x%x\n",
|
||||
cpu, spm_get_firmware_version(), suspend_ctrl.wake_src,
|
||||
mmio_read_32(PCM_CON1));
|
||||
INFO("settle = %u, sec = %u, sw_flag = 0x%x 0x%x, src_req = 0x%x\n",
|
||||
settle, mmio_read_32(PCM_TIMER_VAL) / 32768,
|
||||
suspend_ctrl.pcm_flags, suspend_ctrl.pcm_flags1,
|
||||
mmio_read_32(SPM_SRC_REQ));
|
||||
|
||||
if (!mt_console_uart_cg_status())
|
||||
console_switch_state(CONSOLE_FLAG_RUNTIME);
|
||||
}
|
||||
|
||||
static void go_to_sleep_after_wfi(void)
|
||||
{
|
||||
struct wake_status spm_wakesta;
|
||||
|
||||
if (is_infra_pdn(suspend_ctrl.pcm_flags))
|
||||
mt_uart_restore();
|
||||
|
||||
spm_set_pcm_wdt(0);
|
||||
spm_get_wakeup_status(&spm_wakesta);
|
||||
spm_clean_after_wakeup();
|
||||
|
||||
if (!mt_console_uart_cg_status())
|
||||
console_switch_state(CONSOLE_FLAG_BOOT);
|
||||
|
||||
spm_output_wake_reason(&spm_wakesta, "suspend");
|
||||
|
||||
if (!mt_console_uart_cg_status())
|
||||
console_switch_state(CONSOLE_FLAG_RUNTIME);
|
||||
}
|
||||
|
||||
static void spm_enable_armpll_l(void)
|
||||
{
|
||||
/* power on */
|
||||
mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x1);
|
||||
|
||||
/* clear isolation */
|
||||
mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x2);
|
||||
|
||||
/* enable pll */
|
||||
mmio_setbits_32(ARMPLL_L_CON0, 0x1);
|
||||
|
||||
/* Add 20us delay for turning on PLL */
|
||||
udelay(20);
|
||||
}
|
||||
|
||||
static void spm_disable_armpll_l(void)
|
||||
{
|
||||
/* disable pll */
|
||||
mmio_clrbits_32(ARMPLL_L_CON0, 0x1);
|
||||
|
||||
/* isolation */
|
||||
mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x2);
|
||||
|
||||
/* power off */
|
||||
mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x1);
|
||||
}
|
||||
|
||||
void spm_system_suspend(void)
|
||||
{
|
||||
spm_disable_armpll_l();
|
||||
bcpu_enable(0);
|
||||
bcpu_sram_enable(0);
|
||||
spm_lock_get();
|
||||
go_to_sleep_before_wfi();
|
||||
spm_lock_release();
|
||||
}
|
||||
|
||||
void spm_system_suspend_finish(void)
|
||||
{
|
||||
spm_lock_get();
|
||||
go_to_sleep_after_wfi();
|
||||
spm_lock_release();
|
||||
spm_enable_armpll_l();
|
||||
bcpu_sram_enable(1);
|
||||
bcpu_enable(1);
|
||||
}
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SPM_SUSPEND_H__
|
||||
#define __SPM_SUSPEND_H__
|
||||
|
||||
void spm_system_suspend(void);
|
||||
void spm_system_suspend_finish(void);
|
||||
|
||||
#endif /* __SPM_SUSPEND_H__*/
|
||||
|
|
@ -24,8 +24,6 @@
|
|||
#define BIT_CA15M_L2PARITY_EN (1 << 1)
|
||||
#define BIT_CA15M_LASTPC_DIS (1 << 8)
|
||||
|
||||
#define MP1_CPUTOP_PWR_CON 0x10006218
|
||||
|
||||
#define MCU_ALL_PWR_ON_CTRL 0x0c530b58
|
||||
#define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133
|
||||
#define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define APMIXEDSYS (IO_PHYS + 0xC000)
|
||||
#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200)
|
||||
#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210)
|
||||
#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c)
|
||||
#define MAINPLL_CON0 (APMIXEDSYS + 0x220)
|
||||
#define CCIPLL_CON0 (APMIXEDSYS + 0x290)
|
||||
|
||||
|
|
@ -74,6 +75,7 @@
|
|||
#define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604)
|
||||
#define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0)
|
||||
#define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4)
|
||||
#define EMI_WFIFO (MCUCFG_BASE + 0x0b5c)
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC related constants
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -9,6 +9,7 @@
|
|||
#include <lib/mmio.h>
|
||||
#include <plat_debug.h>
|
||||
#include <platform_def.h>
|
||||
#include <spm.h>
|
||||
|
||||
void circular_buffer_setup(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@
|
|||
#include <plat_private.h>
|
||||
#include <power_tracer.h>
|
||||
#include <pmic.h>
|
||||
#include <spm.h>
|
||||
#include <spm_suspend.h>
|
||||
#include <rtc.h>
|
||||
|
||||
#define MTK_LOCAL_STATE_OFF 2
|
||||
|
|
@ -147,6 +149,54 @@ static void __dead2 plat_mtk_system_reset(void)
|
|||
panic();
|
||||
}
|
||||
|
||||
static void plat_mtk_power_domain_suspend(const psci_power_state_t *state)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
int cpu = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
int cluster = MPIDR_AFFLVL1_VAL(mpidr);
|
||||
|
||||
spm_system_suspend();
|
||||
|
||||
/* init cpu reset arch as AARCH64 */
|
||||
mcucfg_init_archstate(cluster, cpu, 1);
|
||||
mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
|
||||
spm_set_bootaddr(secure_entrypoint);
|
||||
|
||||
/* Prevent interrupts from spuriously waking up this cpu */
|
||||
mt_gic_cpuif_disable();
|
||||
mt_gic_irq_save();
|
||||
|
||||
if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) {
|
||||
plat_mtk_cci_disable();
|
||||
disable_scu(mpidr);
|
||||
}
|
||||
}
|
||||
|
||||
static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
|
||||
mt_gic_init();
|
||||
mt_gic_irq_restore();
|
||||
|
||||
if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) {
|
||||
enable_scu(mpidr);
|
||||
plat_mtk_cci_enable();
|
||||
plat_dcm_restore_cluster_on(mpidr);
|
||||
}
|
||||
|
||||
mmio_write_32(EMI_WFIFO, 0xf);
|
||||
spm_system_suspend_finish();
|
||||
}
|
||||
|
||||
static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state)
|
||||
{
|
||||
assert(PLAT_MAX_PWR_LVL >= 2);
|
||||
|
||||
for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
|
||||
req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* MTK_platform handler called when an affinity instance is about to be turned
|
||||
* on. The level and mpidr determine the affinity instance.
|
||||
|
|
@ -156,12 +206,12 @@ static const plat_psci_ops_t plat_plat_pm_ops = {
|
|||
.pwr_domain_on = plat_mtk_power_domain_on,
|
||||
.pwr_domain_on_finish = plat_mtk_power_domain_on_finish,
|
||||
.pwr_domain_off = plat_mtk_power_domain_off,
|
||||
.pwr_domain_suspend = NULL,
|
||||
.pwr_domain_suspend_finish = NULL,
|
||||
.pwr_domain_suspend = plat_mtk_power_domain_suspend,
|
||||
.pwr_domain_suspend_finish = plat_mtk_power_domain_suspend_finish,
|
||||
.system_off = plat_mtk_system_off,
|
||||
.system_reset = plat_mtk_system_reset,
|
||||
.validate_power_state = NULL,
|
||||
.get_sys_suspend_power_state = NULL,
|
||||
.get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state,
|
||||
};
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
|
|||
-I${MTK_PLAT_SOC}/drivers/spmc/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/gpio/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/pmic/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/spm/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/rtc/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/uart/ \
|
||||
-I${MTK_PLAT_SOC}/include/
|
||||
|
|
@ -47,6 +48,9 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
|
||||
${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
|
||||
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
|
||||
${MTK_PLAT_SOC}/drivers/spm/spm.c \
|
||||
${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \
|
||||
${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \
|
||||
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
|
||||
${MTK_PLAT_SOC}/drivers/uart/uart.c \
|
||||
${MTK_PLAT_SOC}/plat_pm.c \
|
||||
|
|
|
|||
Loading…
Reference in New Issue