mediatek: mt8192: Add SPMC driver
Add SPMC driver for CPU power on/off. Change-Id: I526b98d5885855efce019dd09cfd93b8816cbf19 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
This commit is contained in:
James Liao
Manish Pandey
parent
0b18d5a5d6
commit
3d1e536eea
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <mcucfg.h>
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#include <mtspmc.h>
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#include <mtspmc_private.h>
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void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu)
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{
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
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}
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void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu)
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{
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mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
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}
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void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr)
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{
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assert(cluster == 0U);
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mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr);
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}
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uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu)
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{
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assert(cluster == 0U);
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return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR));
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}
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void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64)
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{
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uint32_t reg;
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assert(cluster == 0U);
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reg = per_cluster(cluster, MCUCFG_INITARCH);
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if (arm64) {
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mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
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} else {
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mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
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}
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}
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/**
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* Return subsystem's power state.
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*
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* @mask: mask to SPM_CPU_PWR_STATUS to query the power state
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* of one subsystem.
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* RETURNS:
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* 0 (the subsys was powered off)
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* 1 (the subsys was powered on)
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*/
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bool spm_get_powerstate(uint32_t mask)
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{
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return (mmio_read_32(SPM_CPU_PWR_STATUS) & mask) != 0U;
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}
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bool spm_get_cluster_powerstate(uint32_t cluster)
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{
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assert(cluster == 0U);
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return spm_get_powerstate(MP0_CPUTOP);
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}
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bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu)
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{
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uint32_t mask = BIT(cpu);
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assert(cluster == 0U);
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return spm_get_powerstate(mask);
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}
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int spmc_init(void)
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{
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INFO("SPM: enable CPC mode\n");
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mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
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mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B);
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(1));
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(2));
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(3));
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(4));
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(5));
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(6));
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(7));
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mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
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mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
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mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG);
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE);
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return 0;
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}
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/**
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* Power on a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered on
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* @cpu: the CPU ID of the CPU which to be powered on
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*/
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void spm_poweron_cpu(uint32_t cluster, uint32_t cpu)
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{
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/* set to 0 after BIG VPROC bulk on & before B-core power on seq. */
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if (cpu >= 4U) {
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mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U);
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}
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mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN);
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mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
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while (!spm_get_cpu_powerstate(cluster, cpu)) {
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}
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mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN);
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/* Enable Big CPU Last PC */
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if (cpu >= 4U) {
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mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3));
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}
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}
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/**
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* Power off a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered off
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* @cpu: the CPU ID of the CPU which to be powered off
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*/
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void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu)
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{
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/* Set mp0_spmc_pwr_on_cpuX = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
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}
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/**
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* Power off a cluster with specified index
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*
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* @cluster: the cluster index which to be powered off
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*/
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void spm_poweroff_cluster(uint32_t cluster)
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{
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/* No need to power on/off cluster on single cluster platform */
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assert(false);
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}
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/**
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* Power on a cluster with specified index
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*
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* @cluster: the cluster index which to be powered on
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*/
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void spm_poweron_cluster(uint32_t cluster)
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{
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/* No need to power on/off cluster on single cluster platform */
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assert(false);
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}
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTSPMC_H
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#define MTSPMC_H
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#include <stdint.h>
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int spmc_init(void);
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void spm_poweron_cpu(uint32_t cluster, uint32_t cpu);
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void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu);
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void spm_poweroff_cluster(uint32_t cluster);
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void spm_poweron_cluster(uint32_t cluster);
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bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu);
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bool spm_get_cluster_powerstate(uint32_t cluster);
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bool spm_get_powerstate(uint32_t mask);
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void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64);
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void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr);
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uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu);
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void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu);
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void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu);
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#endif /* MTSPMC_H */
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTSPMC_PRIVATE_H
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#define MTSPMC_PRIVATE_H
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#include <lib/utils_def.h>
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#include <platform_def.h>
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unsigned long read_cpuectlr(void);
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void write_cpuectlr(unsigned long cpuectlr);
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unsigned long read_cpupwrctlr_el1(void);
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void write_cpupwrctlr_el1(unsigned long cpuectlr);
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/*
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* per_cpu/cluster helper
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*/
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struct per_cpu_reg {
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unsigned int cluster_addr;
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unsigned int cpu_stride;
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};
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#define per_cpu(cluster, cpu, reg) \
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(reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
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#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
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#define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
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#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
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#define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
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/* === SPMC related registers */
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#define SPM_POWERON_CONFIG_EN SPM_REG(0x000)
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/* bit-fields of SPM_POWERON_CONFIG_EN */
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#define PROJECT_CODE (U(0xb16) << 16)
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#define BCLK_CG_EN BIT(0)
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#define SPM_PWR_STATUS SPM_REG(0x16c)
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#define SPM_PWR_STATUS_2ND SPM_REG(0x170)
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#define SPM_CPU_PWR_STATUS SPM_REG(0x174)
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/* bit-fields of SPM_PWR_STATUS */
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#define MD BIT(0)
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#define CONN BIT(1)
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#define DDRPHY BIT(2)
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#define DISP BIT(3)
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#define MFG BIT(4)
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#define ISP BIT(5)
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#define INFRA BIT(6)
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#define VDEC BIT(7)
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#define MP0_CPUTOP BIT(8)
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#define MP0_CPU0 BIT(9)
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#define MP0_CPU1 BIT(10)
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#define MP0_CPU2 BIT(11)
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#define MP0_CPU3 BIT(12)
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#define MCUSYS BIT(14)
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#define MP0_CPU4 BIT(15)
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#define MP0_CPU5 BIT(16)
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#define MP0_CPU6 BIT(17)
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#define MP0_CPU7 BIT(18)
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#define VEN BIT(21)
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/* === SPMC related registers */
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#define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
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#define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
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#define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
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#define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
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#define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
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#define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
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#define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
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#define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
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#define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
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#define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224)
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/* bit fields of SPM_*_PWR_CON */
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#define PWR_ON_ACK BIT(31)
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#define VPROC_EXT_OFF BIT(7)
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#define DORMANT_EN BIT(6)
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#define RESETPWRON_CONFIG BIT(5)
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#define PWR_CLK_DIS BIT(4)
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#define PWR_ON BIT(2)
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#define PWR_RST_B BIT(0)
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/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
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static const struct per_cpu_reg SPM_CPU_PWR[] = {
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{ .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
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};
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/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
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static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
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{ .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
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};
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/* === MCUCFG related registers */
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/* aa64naa32 */
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#define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4)
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/* reset vectors */
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#define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900)
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#define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908)
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#define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910)
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#define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918)
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#define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920)
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#define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928)
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#define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930)
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#define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938)
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/* MCUSYS DREQ BIG VPROC ISO control */
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#define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c)
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/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
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static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
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{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
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};
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/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
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static const struct per_cpu_reg MCUCFG_INITARCH[] = {
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{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
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};
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#define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu)
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#define LAST_PC_REG(cpu) (MCUCFG_REG(0x308) + (cpu * 0x800))
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/* === CPC control */
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#define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
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#define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840)
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/* bit fields of CPC_FLOW_CTRL_CFG */
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#define CPC_CTRL_ENABLE BIT(16)
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#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
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#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu)
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/* bit fields of CPC_SPMC_PWR_STATUS */
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#define CORE_SPMC_PWR_ON_ACK GENMASK(15, 0)
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/* === APB Module infracfg_ao */
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#define INFRA_TOPAXI_PROTECTEN INFRACFG_AO_REG(0x0220)
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#define INFRA_TOPAXI_PROTECTEN_STA0 INFRACFG_AO_REG(0x0224)
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#define INFRA_TOPAXI_PROTECTEN_STA1 INFRACFG_AO_REG(0x0228)
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#define INFRA_TOPAXI_PROTECTEN_SET INFRACFG_AO_REG(0x02a0)
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#define INFRA_TOPAXI_PROTECTEN_CLR INFRACFG_AO_REG(0x02a4)
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#define INFRA_TOPAXI_PROTECTEN_1 INFRACFG_AO_REG(0x0250)
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#define INFRA_TOPAXI_PROTECTEN_STA0_1 INFRACFG_AO_REG(0x0254)
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#define INFRA_TOPAXI_PROTECTEN_STA1_1 INFRACFG_AO_REG(0x0258)
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#define INFRA_TOPAXI_PROTECTEN_1_SET INFRACFG_AO_REG(0x02a8)
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#define INFRA_TOPAXI_PROTECTEN_1_CLR INFRACFG_AO_REG(0x02ac)
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/* bit fields of INFRA_TOPAXI_PROTECTEN */
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#define MP0_SPMC_PROT_STEP1_0_MASK BIT(12)
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#define MP0_SPMC_PROT_STEP1_1_MASK (BIT(26) | BIT(12))
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/* === SPARK */
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#define VOLTAGE_04 U(0x40)
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#define VOLTAGE_05 U(0x60)
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#define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200)
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#define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334)
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#define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340)
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/* bit fields of CPU0_ILDO_CONTROL5 */
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#define ILDO_RET_VOSEL GENMASK(7, 0)
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/* bit fields of PTP3_CPU_SPMC_SW_CFG */
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#define SW_SPARK_EN BIT(0)
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/* bit fields of CPU0_ILDO_CONTROL8 */
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#define ILDO_BYPASS_B BIT(0)
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static const struct per_cpu_reg MCUCFG_SPARK[] = {
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{ .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
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};
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static const struct per_cpu_reg ILDO_CONTROL5[] = {
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{ .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
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};
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static const struct per_cpu_reg ILDO_CONTROL8[] = {
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{ .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
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};
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#endif /* MTSPMC_PRIVATE_H */
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@ -0,0 +1,257 @@
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/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MCUCFG_H
|
||||
#define MCUCFG_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
|
||||
|
||||
#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
|
||||
#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
|
||||
|
||||
#define MP2_CPUCFG MCUCFG_REG(0x2208)
|
||||
|
||||
#define MP2_CPU0_STANDBYWFE BIT(4)
|
||||
#define MP2_CPU1_STANDBYWFE BIT(5)
|
||||
|
||||
#define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788)
|
||||
#define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C)
|
||||
#define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790)
|
||||
|
||||
#define sw_spark_en BIT(0)
|
||||
#define sw_no_wait_for_q_channel BIT(1)
|
||||
#define sw_fsm_override BIT(2)
|
||||
#define sw_logic_pre1_pdb BIT(3)
|
||||
#define sw_logic_pre2_pdb BIT(4)
|
||||
#define sw_logic_pdb BIT(5)
|
||||
#define sw_iso BIT(6)
|
||||
#define sw_sram_sleepb (U(0x3F) << 7)
|
||||
#define sw_sram_isointb BIT(13)
|
||||
#define sw_clk_dis BIT(14)
|
||||
#define sw_ckiso BIT(15)
|
||||
#define sw_pd (U(0x3F) << 16)
|
||||
#define sw_hot_plug_reset BIT(22)
|
||||
#define sw_pwr_on_override_en BIT(23)
|
||||
#define sw_pwr_on BIT(24)
|
||||
#define sw_coq_dis BIT(25)
|
||||
#define logic_pdbo_all_off_ack BIT(26)
|
||||
#define logic_pdbo_all_on_ack BIT(27)
|
||||
#define logic_pre2_pdbo_all_on_ack BIT(28)
|
||||
#define logic_pre1_pdbo_all_on_ack BIT(29)
|
||||
|
||||
|
||||
#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
|
||||
(MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
|
||||
|
||||
#define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30)
|
||||
#define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34)
|
||||
#define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38)
|
||||
#define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C)
|
||||
|
||||
#define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30)
|
||||
#define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34)
|
||||
#define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38)
|
||||
#define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C)
|
||||
|
||||
#define cpu_sw_spark_en BIT(0)
|
||||
#define cpu_sw_no_wait_for_q_channel BIT(1)
|
||||
#define cpu_sw_fsm_override BIT(2)
|
||||
#define cpu_sw_logic_pre1_pdb BIT(3)
|
||||
#define cpu_sw_logic_pre2_pdb BIT(4)
|
||||
#define cpu_sw_logic_pdb BIT(5)
|
||||
#define cpu_sw_iso BIT(6)
|
||||
#define cpu_sw_sram_sleepb BIT(7)
|
||||
#define cpu_sw_sram_isointb BIT(8)
|
||||
#define cpu_sw_clk_dis BIT(9)
|
||||
#define cpu_sw_ckiso BIT(10)
|
||||
#define cpu_sw_pd (U(0x1F) << 11)
|
||||
#define cpu_sw_hot_plug_reset BIT(16)
|
||||
#define cpu_sw_powr_on_override_en BIT(17)
|
||||
#define cpu_sw_pwr_on BIT(18)
|
||||
#define cpu_spark2ldo_allswoff BIT(19)
|
||||
#define cpu_pdbo_all_on_ack BIT(20)
|
||||
#define cpu_pre2_pdbo_allon_ack BIT(21)
|
||||
#define cpu_pre1_pdbo_allon_ack BIT(22)
|
||||
|
||||
/* CPC related registers */
|
||||
#define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714)
|
||||
#define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804)
|
||||
#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
|
||||
#define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818)
|
||||
#define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c)
|
||||
#define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824)
|
||||
#define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8)
|
||||
#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac)
|
||||
#define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04)
|
||||
#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c)
|
||||
#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10)
|
||||
#define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14)
|
||||
#define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70)
|
||||
#define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74)
|
||||
|
||||
#define SPARK2LDO MCUCFG_REG(0x2700)
|
||||
/* APB Module mcucfg */
|
||||
#define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000)
|
||||
#define MP0_AXI_CONFIG MCUCFG_REG(0x02C)
|
||||
#define MP0_MISC_CONFIG0 MCUCFG_REG(0x030)
|
||||
#define MP0_MISC_CONFIG1 MCUCFG_REG(0x034)
|
||||
#define MP0_MISC_CONFIG2 MCUCFG_REG(0x038)
|
||||
#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8))
|
||||
#define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C)
|
||||
#define MP0_MISC_CONFIG9 MCUCFG_REG(0x054)
|
||||
#define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064)
|
||||
|
||||
#define MP0_RW_RSVD0 MCUCFG_REG(0x06C)
|
||||
|
||||
|
||||
#define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200)
|
||||
#define MP1_AXI_CONFIG MCUCFG_REG(0x22C)
|
||||
#define MP1_MISC_CONFIG0 MCUCFG_REG(0x230)
|
||||
#define MP1_MISC_CONFIG1 MCUCFG_REG(0x234)
|
||||
#define MP1_MISC_CONFIG2 MCUCFG_REG(0x238)
|
||||
#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8))
|
||||
#define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C)
|
||||
#define MP1_MISC_CONFIG9 MCUCFG_REG(0x254)
|
||||
#define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264)
|
||||
|
||||
#define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740)
|
||||
#define SYNC_DCM_CONFIG MCUCFG_REG(0x744)
|
||||
|
||||
#define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0)
|
||||
|
||||
#define MP0_SPMC MCUCFG_REG(0x788)
|
||||
#define MP1_SPMC MCUCFG_REG(0x78C)
|
||||
#define MP2_AXI_CONFIG MCUCFG_REG(0x220C)
|
||||
#define MP2_AXI_CONFIG_ACINACTM BIT(0)
|
||||
#define MP2_AXI_CONFIG_AINACTS BIT(4)
|
||||
|
||||
#define MPx_AXI_CONFIG_ACINACTM BIT(4)
|
||||
#define MPx_AXI_CONFIG_AINACTS BIT(5)
|
||||
|
||||
#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28)
|
||||
|
||||
#define MP0_CPU0_STANDBYWFE BIT(20)
|
||||
#define MP0_CPU1_STANDBYWFE BIT(21)
|
||||
#define MP0_CPU2_STANDBYWFE BIT(22)
|
||||
#define MP0_CPU3_STANDBYWFE BIT(23)
|
||||
|
||||
#define MP1_CPU0_STANDBYWFE BIT(20)
|
||||
#define MP1_CPU1_STANDBYWFE BIT(21)
|
||||
#define MP1_CPU2_STANDBYWFE BIT(22)
|
||||
#define MP1_CPU3_STANDBYWFE BIT(23)
|
||||
|
||||
#define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00)
|
||||
#define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04)
|
||||
#define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08)
|
||||
#define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00)
|
||||
#define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04)
|
||||
#define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08)
|
||||
|
||||
#define MP2_PWR_RST_CTL MCUCFG_REG(0x2008)
|
||||
#define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0)
|
||||
#define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4)
|
||||
|
||||
#define MP2_COQ MCUCFG_REG(0x22BC)
|
||||
#define MP2_COQ_SW_DIS BIT(0)
|
||||
|
||||
#define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400)
|
||||
#define MP2_CA15M_MON_L MCUCFG_REG(0x2404)
|
||||
|
||||
#define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430)
|
||||
#define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438)
|
||||
#define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434)
|
||||
#define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C)
|
||||
|
||||
#define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068)
|
||||
#define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268)
|
||||
#define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C)
|
||||
|
||||
#define MP2_SW_RST_B BIT(0)
|
||||
#define MP2_TOPAON_APB_MASK BIT(1)
|
||||
|
||||
#define B_SW_HOT_PLUG_RESET BIT(30)
|
||||
|
||||
#define B_SW_PD_OFFSET 18U
|
||||
#define B_SW_PD (U(0x3f) << B_SW_PD_OFFSET)
|
||||
|
||||
#define B_SW_SRAM_SLEEPB_OFFSET 12U
|
||||
#define B_SW_SRAM_SLEEPB (U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET)
|
||||
|
||||
#define B_SW_SRAM_ISOINTB BIT(9)
|
||||
#define B_SW_ISO BIT(8)
|
||||
#define B_SW_LOGIC_PDB BIT(7)
|
||||
#define B_SW_LOGIC_PRE2_PDB BIT(6)
|
||||
#define B_SW_LOGIC_PRE1_PDB BIT(5)
|
||||
#define B_SW_FSM_OVERRIDE BIT(4)
|
||||
#define B_SW_PWR_ON BIT(3)
|
||||
#define B_SW_PWR_ON_OVERRIDE_EN BIT(2)
|
||||
|
||||
#define B_FSM_STATE_OUT_OFFSET (6U)
|
||||
#define B_FSM_STATE_OUT_MASK (U(0x1f) << B_FSM_STATE_OUT_OFFSET)
|
||||
#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5)
|
||||
#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4)
|
||||
#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3)
|
||||
#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2)
|
||||
|
||||
#define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET)
|
||||
#define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET)
|
||||
#define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* cpu boot mode */
|
||||
enum {
|
||||
MP0_CPUCFG_64BIT_SHIFT = 12U,
|
||||
MP1_CPUCFG_64BIT_SHIFT = 28U,
|
||||
MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT,
|
||||
MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT
|
||||
};
|
||||
|
||||
enum {
|
||||
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U,
|
||||
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U,
|
||||
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U,
|
||||
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U,
|
||||
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U,
|
||||
|
||||
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
|
||||
U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
|
||||
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
|
||||
U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
|
||||
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
|
||||
U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
|
||||
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
|
||||
U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
|
||||
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
|
||||
U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
|
||||
};
|
||||
|
||||
enum {
|
||||
MP1_AINACTS_SHIFT = 4U,
|
||||
MP1_AINACTS = 1U << MP1_AINACTS_SHIFT
|
||||
};
|
||||
|
||||
enum {
|
||||
MP1_SW_CG_GEN_SHIFT = 12U,
|
||||
MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT
|
||||
};
|
||||
|
||||
enum {
|
||||
MP1_L2RSTDISABLE_SHIFT = 14U,
|
||||
MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT
|
||||
};
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* MCUCFG_H */
|
||||
|
|
@ -25,6 +25,7 @@
|
|||
#define MTK_DEV_RNG2_SIZE 0x600000
|
||||
|
||||
#define GPIO_BASE (IO_PHYS + 0x00005000)
|
||||
#define SPM_BASE (IO_PHYS + 0x00006000)
|
||||
#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
|
||||
#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
|
||||
#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
|
|||
-I${MTK_PLAT_SOC}/include/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/gpio/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/spmc/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/timer/
|
||||
|
||||
GICV3_SUPPORT_GIC600 := 1
|
||||
|
|
@ -39,9 +40,9 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT_SOC}/plat_mt_gic.c \
|
||||
${MTK_PLAT_SOC}/plat_mt_cirq.c \
|
||||
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
|
||||
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
|
||||
${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
|
||||
|
||||
|
||||
# Configs for A76 and A55
|
||||
HW_ASSISTED_COHERENCY := 1
|
||||
USE_COHERENT_MEM := 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue