feat(gic600ae_fmu): disable SMID for unavailable blocks
This patch updates the gic600_fmu_init function to disable all safety mechanisms for a block ID that is not present on the platform. All safety mechanisms for GIC-600AE are enabled by default and should be disabled for blocks that are not present on the platform to avoid false positive RAS errors. Change-Id: I52dc3bee9a8b49fd2e51d7ed851fdc803a48e6e3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -268,8 +268,12 @@ void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask,
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/* Enable error detection for all error records */
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/* Enable error detection for all error records */
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for (unsigned int i = 0U; i < num_blk; i++) {
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for (unsigned int i = 0U; i < num_blk; i++) {
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/* Skip next steps if the block is not present */
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/*
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* Disable all safety mechanisms for blocks that are not
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* present and skip the next steps.
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*/
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if ((blk_present_mask & BIT(i)) == 0U) {
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if ((blk_present_mask & BIT(i)) == 0U) {
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gic_fmu_disable_all_sm_blkid(base, i);
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continue;
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continue;
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -258,3 +258,47 @@ void gic_fmu_write_pingmask(uintptr_t base, uint64_t val)
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{
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{
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GIC_FMU_WRITE_64(base, GICFMU_PINGMASK, 0, val);
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GIC_FMU_WRITE_64(base, GICFMU_PINGMASK, 0, val);
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}
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}
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/*
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* Helper function to disable all safety mechanisms for a given block
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*/
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void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid)
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{
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uint32_t smen, max_smid = U(0);
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/* Sanity check block ID */
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assert((blkid >= FMU_BLK_GICD) && (blkid <= FMU_BLK_PPI31));
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/* Find the max safety mechanism ID for the block */
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switch (blkid) {
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case FMU_BLK_GICD:
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max_smid = FMU_SMID_GICD_MAX;
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break;
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case FMU_BLK_SPICOL:
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max_smid = FMU_SMID_SPICOL_MAX;
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break;
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case FMU_BLK_WAKERQ:
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max_smid = FMU_SMID_WAKERQ_MAX;
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break;
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case FMU_BLK_ITS0...FMU_BLK_ITS7:
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max_smid = FMU_SMID_ITS_MAX;
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break;
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case FMU_BLK_PPI0...FMU_BLK_PPI31:
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max_smid = FMU_SMID_PPI_MAX;
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break;
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default:
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assert(false);
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break;
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}
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/* Disable all Safety Mechanisms for a given block id */
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for (unsigned int i = 0U; i < max_smid; i++) {
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smen = (blkid << FMU_SMEN_BLK_SHIFT) | (i << FMU_SMEN_SMID_SHIFT);
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gic_fmu_write_smen(base, smen);
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -86,10 +86,10 @@
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/* Safety Mechamism limit */
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/* Safety Mechamism limit */
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#define FMU_SMID_GICD_MAX U(33)
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#define FMU_SMID_GICD_MAX U(33)
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#define FMU_SMID_PPI_MAX U(12)
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#define FMU_SMID_ITS_MAX U(14)
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#define FMU_SMID_SPICOL_MAX U(5)
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#define FMU_SMID_SPICOL_MAX U(5)
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#define FMU_SMID_WAKERQ_MAX U(2)
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#define FMU_SMID_WAKERQ_MAX U(2)
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#define FMU_SMID_ITS_MAX U(14)
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#define FMU_SMID_PPI_MAX U(12)
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/* MBIST Safety Mechanism ID */
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/* MBIST Safety Mechanism ID */
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#define GICD_MBIST_REQ_ERROR U(23)
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#define GICD_MBIST_REQ_ERROR U(23)
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@ -142,6 +142,7 @@ void gic_fmu_write_pingnow(uintptr_t base, uint32_t val);
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void gic_fmu_write_smen(uintptr_t base, uint32_t val);
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void gic_fmu_write_smen(uintptr_t base, uint32_t val);
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void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val);
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void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val);
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void gic_fmu_write_pingmask(uintptr_t base, uint64_t val);
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void gic_fmu_write_pingmask(uintptr_t base, uint64_t val);
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void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid);
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void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en);
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void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en);
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void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask,
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void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask,
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