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intel: Platform common code refactor 

Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
This commit is contained in:
Hadi Asyrafi 2019-08-01 14:48:39 +08:00 committed by Sandrine Bailleux
parent d8820789ca
commit 3f7b1490dc
21 changed files with 21 additions and 266 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
plat/intel/soc/agilex/include/platform_def.h
View File

@ -15,7 +15,7 @@
#define PLAT_CPUID_RELEASE 0xffe1b000
#define PLAT_AGX_SEC_ENTRY 0xffe1b008
#define PLAT_SEC_ENTRY 0xffe1b008
/* Define next boot image name and offset */
#define PLAT_NS_IMAGE_OFFSET 0x50000

7
plat/intel/soc/agilex/platform.mk
View File

@ -7,7 +7,8 @@
#
PLAT_INCLUDES := \
-Iplat/intel/soc/agilex/include/ \
-Iplat/intel/soc/common/drivers/
-Iplat/intel/soc/common/drivers/ \
-Iplat/intel/soc/common/include/
PLAT_BL_COMMON_SOURCES := \
drivers/arm/gic/common/gic_common.c \
@ -19,8 +20,8 @@ PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
plat/common/plat_gicv2.c \
plat/intel/soc/agilex/aarch64/platform_common.c \
plat/intel/soc/agilex/aarch64/plat_helpers.S \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S
BL2_SOURCES += \
common/desc_image_load.c \

2
plat/intel/soc/agilex/socfpga_psci.c
View File

@ -17,7 +17,7 @@
#define AGX_RSTMGR_OFST 0xffd11000
#define AGX_RSTMGR_MPUMODRST_OFST 0x20
uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_AGX_SEC_ENTRY;
uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
/*******************************************************************************

4
plat/intel/soc/agilex/aarch64/plat_helpers.S → plat/intel/soc/common/aarch64/plat_helpers.S
View File

@ -34,7 +34,7 @@ func plat_secondary_cold_boot_setup
poll_mailbox:
wfi
mov_imm x0, PLAT_AGX_SEC_ENTRY
mov_imm x0, PLAT_SEC_ENTRY
ldr x1, [x0]
mov_imm x2, PLAT_CPUID_RELEASE
ldr x3, [x2]
@ -66,7 +66,7 @@ func plat_my_core_pos
endfunc plat_my_core_pos
func plat_get_my_entrypoint
mov_imm x1, PLAT_AGX_SEC_ENTRY
mov_imm x1, PLAT_SEC_ENTRY
ldr x0, [x1]
ret
endfunc plat_get_my_entrypoint

0
plat/intel/soc/agilex/aarch64/platform_common.c → plat/intel/soc/common/aarch64/platform_common.c
View File

0
plat/intel/soc/agilex/include/plat_macros.S → plat/intel/soc/common/include/plat_macros.S
View File

0
plat/intel/soc/agilex/include/socfpga_private.h → plat/intel/soc/common/include/socfpga_private.h
View File

121
plat/intel/soc/stratix10/aarch64/plat_helpers.S
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@ -1,121 +0,0 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <cpu_macros.S>
#include <platform_def.h>
.globl plat_secondary_cold_boot_setup
.globl platform_is_primary_cpu
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_crash_console_flush
.globl platform_mem_init
.globl plat_get_my_entrypoint
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* This function performs any platform specific actions
* needed for a secondary cpu after a cold reset e.g
* mark the cpu's presence, mechanism to place it in a
* holding pen etc.
* -----------------------------------------------------
*/
func plat_secondary_cold_boot_setup
/* Wait until the it gets reset signal from rstmgr gets populated */
poll_mailbox:
wfi
mov_imm x0, PLAT_S10_SEC_ENTRY
ldr x1, [x0]
mov_imm x2, PLAT_CPUID_RELEASE
ldr x3, [x2]
mrs x4, mpidr_el1
and x4, x4, #0xff
cmp x3, x4
b.ne poll_mailbox
br x1
endfunc plat_secondary_cold_boot_setup
func platform_is_primary_cpu
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
cmp x0, #PLAT_PRIMARY_CPU
cset x0, eq
ret
endfunc platform_is_primary_cpu
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
b platform_is_primary_cpu
endfunc plat_is_my_cpu_primary
func plat_my_core_pos
mrs x0, mpidr_el1
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #6
ret
endfunc plat_my_core_pos
func plat_get_my_entrypoint
mov_imm x1, PLAT_S10_SEC_ENTRY
ldr x0, [x1]
ret
endfunc plat_get_my_entrypoint
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
* without a C Runtime to print crash report.
* Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func plat_crash_console_init
mov_imm x0, PLAT_UART0_BASE
mov_imm x1, PLAT_UART_CLOCK
mov_imm x2, PLAT_BAUDRATE
b console_16550_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
* int plat_crash_console_putc(void)
* Function to print a character on the crash
* console without a C Runtime.
* Clobber list : x1, x2
* ---------------------------------------------
*/
func plat_crash_console_putc
mov_imm x1, PLAT_UART0_BASE
b console_16550_core_putc
endfunc plat_crash_console_putc
func plat_crash_console_flush
mov_imm x0, CRASH_CONSOLE_BASE
b console_16550_core_flush
endfunc plat_crash_console_flush
/* --------------------------------------------------------
* void platform_mem_init (void);
*
* Any memory init, relocation to be done before the
* platform boots. Called very early in the boot process.
* --------------------------------------------------------
*/
func platform_mem_init
mov x0, #0
ret
endfunc platform_mem_init
.data
.align 3

57
plat/intel/soc/stratix10/aarch64/platform_common.c
View File

@ -1,57 +0,0 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <lib/mmio.h>
#include <platform_def.h>
unsigned int plat_get_syscnt_freq2(void)
{
return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
}
unsigned long plat_get_ns_image_entrypoint(void)
{
return PLAT_NS_IMAGE_OFFSET;
}
/******************************************************************************
* Gets SPSR for BL32 entry
*****************************************************************************/
uint32_t plat_get_spsr_for_bl32_entry(void)
{
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL32 image.
*/
return 0;
}
/******************************************************************************
* Gets SPSR for BL33 entry
*****************************************************************************/
uint32_t plat_get_spsr_for_bl33_entry(void)
{
unsigned long el_status;
unsigned int mode;
uint32_t spsr;
/* Figure out what mode we enter the non-secure world in */
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
el_status &= ID_AA64PFR0_ELX_MASK;
mode = (el_status) ? MODE_EL2 : MODE_EL1;
/*
* TODO: Consider the possibility of specifying the SPSR in
* the FIP ToC and allowing the platform to have a say as
* well.
*/
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
return spsr;
}

6
plat/intel/soc/stratix10/bl2_plat_setup.c
View File

@ -19,7 +19,7 @@
#include <common/image_decompress.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <platform_private.h>
#include <socfpga_private.h>
#include <drivers/synopsys/dw_mmc.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
@ -29,7 +29,7 @@
#include "s10_clock_manager.h"
#include "s10_handoff.h"
#include "s10_pinmux.h"
#include "aarch64/stratix10_private.h"
#include "stratix10_private.h"
#include "include/s10_mailbox.h"
#include "qspi/cadence_qspi.h"
#include "wdt/watchdog.h"
@ -78,7 +78,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
&console);
plat_delay_timer_init();
socfpga_delay_timer_init();
init_hard_memory_controller();
}

3
plat/intel/soc/stratix10/bl31_plat_setup.c
View File

@ -21,9 +21,8 @@
#include <lib/mmio.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <platform_private.h>
#include "aarch64/stratix10_private.h"
#include "stratix10_private.h"
#include "s10_handoff.h"
#include "s10_reset_manager.h"
#include "s10_memory_controller.h"

22
plat/intel/soc/stratix10/include/plat_macros.S
View File

@ -1,22 +0,0 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLAT_MACROS_S__
#define __PLAT_MACROS_S__
#include <platform_def.h>
/* ---------------------------------------------
* The below required platform porting macro
* prints out relevant platform registers
* whenever an unhandled exception is taken in
* BL31.
* ---------------------------------------------
*/
.macro plat_crash_print_regs
.endm
#endif /* __PLAT_MACROS_S__ */

2
plat/intel/soc/stratix10/platform_def.h → plat/intel/soc/stratix10/include/platform_def.h
View File

@ -16,7 +16,7 @@
#define PLAT_CPUID_RELEASE 0xffe1b000
#define PLAT_S10_SEC_ENTRY 0xffe1b008
#define PLAT_SEC_ENTRY 0xffe1b008
/* Define next boot image name and offset */
#define PLAT_NS_IMAGE_OFFSET 0x50000

41
plat/intel/soc/stratix10/include/platform_private.h
View File

@ -1,41 +0,0 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLATFORM_PRIVATE_H__
#define __PLATFORM_PRIVATE_H__
#include <common/bl_common.h>
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void plat_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit,
unsigned long coh_start,
unsigned long coh_limit);
void plat_configure_mmu_el1(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
unsigned long ro_limit,
unsigned long coh_start,
unsigned long coh_limit);
void plat_gic_driver_init(void);
void plat_arm_gic_init(void);
void plat_delay_timer_init(void);
unsigned long plat_get_ns_image_entrypoint(void);
uint32_t plat_get_spsr_for_bl32_entry(void);
uint32_t plat_get_spsr_for_bl33_entry(void);
#endif /* __PLATFORM_PRIVATE_H__ */

0
plat/intel/soc/stratix10/aarch64/stratix10_private.h → plat/intel/soc/stratix10/include/stratix10_private.h
View File

3
plat/intel/soc/stratix10/plat_psci.c
View File

@ -15,14 +15,13 @@
#include <lib/psci/psci.h>
#include "platform_def.h"
#include "platform_private.h"
#include "s10_reset_manager.h"
#include "s10_mailbox.h"
#define S10_RSTMGR_OFST 0xffd11000
#define S10_RSTMGR_MPUMODRST_OFST 0x20
uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_S10_SEC_ENTRY;
uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
/*******************************************************************************

2
plat/intel/soc/stratix10/plat_storage.c
View File

@ -21,7 +21,7 @@
#include <lib/utils.h>
#include <common/tbbr/tbbr_img_def.h>
#include "platform_def.h"
#include "aarch64/stratix10_private.h"
#include "stratix10_private.h"
#define STRATIX10_FIP_BASE (0)
#define STRATIX10_FIP_MAX_SIZE (0x1000000)

12
plat/intel/soc/stratix10/platform.mk
View File

@ -5,9 +5,9 @@
#
PLAT_INCLUDES := \
-Iplat/intel/soc/stratix10/ \
-Iplat/intel/soc/stratix10/include/ \
-Iplat/intel/soc/common/drivers/
-Iplat/intel/soc/common/drivers/ \
-Iplat/intel/soc/common/include/
PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/xlat_tables_common.c \
@ -15,12 +15,12 @@ PLAT_BL_COMMON_SOURCES := \
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
plat/common/plat_gicv2.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
plat/intel/soc/stratix10/aarch64/platform_common.c \
plat/intel/soc/stratix10/aarch64/plat_helpers.S \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S
BL2_SOURCES += \
drivers/partition/partition.c \
@ -64,7 +64,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c\
plat/intel/soc/stratix10/soc/s10_handoff.c \
plat/intel/soc/stratix10/soc/s10_mailbox.c \
plat/intel/soc/stratix10/soc/s10_mailbox.c
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1

1
plat/intel/soc/stratix10/soc/s10_clock_manager.c
View File

@ -10,7 +10,6 @@
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <platform_def.h>
#include <platform_private.h>
#include "s10_clock_manager.h"
#include "s10_handoff.h"

1
plat/intel/soc/stratix10/soc/s10_handoff.c
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@ -13,7 +13,6 @@
#include <string.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <platform_private.h>
#include "s10_handoff.h"

1
plat/intel/soc/stratix10/soc/s10_reset_manager.c
View File

@ -14,7 +14,6 @@
#include <lib/mmio.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <platform_private.h>
#include "s10_reset_manager.h"
void deassert_peripheral_reset(void)