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refactor(drivers/marvell/comphy-3700): unify Generation Settings register values 

Generation Settings registers have the same layout for different
generations and same setting (i.e. Generation 2 Settings 2 register has
the same layout as Generation 3 Settings 2).

So it does not make sense to prefix the constants for Settings 2 with
G3.

Instead change the prefixes to GSx_ for settings register x.

For Settings 2 of Gen 2 and Gen 3 we have some definitions in the first
and some in the second. Move them all to the first defined register (in
this case Gen 2, since the constant for Gen 1 is not defined because it
is not used).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I15c337eb58aa37fd99fe388fd59373aa325a3a92
This commit is contained in:
Marek Behún 2021-12-08 01:12:00 +01:00
parent 30264e9788
commit 3f9a089297
2 changed files with 22 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -685,16 +685,16 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
* 6. Set G2 Spread Spectrum Clock Amplitude at 4K
*/
usb3_reg_set(reg_base, COMPHY_GEN2_SET2,
G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK);
GS2_TX_SSC_AMP_VALUE_20, GS2_TX_SSC_AMP_MASK);
/*
* 7. Unset G3 Spread Spectrum Clock Amplitude
* set G3 TX and RX Register Master Current Select
*/
mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
RSVD_PH03FH_6_0_MASK;
mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK |
GS2_RSVD_6_0_MASK;
usb3_reg_set(reg_base, COMPHY_GEN3_SET2,
G3_VREG_RXTX_MAS_ISET_60U, mask);
GS2_VREG_RXTX_MAS_ISET_60U, mask);
/*
* 8. Check crystal jumper setting and program the Power and PLL Control
@ -770,7 +770,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
* 15. Set capacitor value for FFE gain peaking to 0xF
*/
usb3_reg_set(reg_base, COMPHY_GEN2_SET3,
COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK);
GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK);
/*
* 16. Release SW reset

38
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -98,28 +98,24 @@ enum {
#define COMPHY_GEN2_SET2 0x3e
#define GEN2_SET2_ADDR(unit) (COMPHY_GEN2_SET2 * PHY_SHFT(unit))
#define G2_TX_SSC_AMP_VALUE_20 BIT(14)
#define G2_TX_SSC_AMP_OFF 9
#define G2_TX_SSC_AMP_LEN 7
#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
G2_TX_SSC_AMP_OFF)
#define GS2_TX_SSC_AMP_VALUE_20 BIT(14)
#define GS2_TX_SSC_AMP_OFF 9
#define GS2_TX_SSC_AMP_LEN 7
#define GS2_TX_SSC_AMP_MASK (((1 << GS2_TX_SSC_AMP_LEN) - 1) << \
GS2_TX_SSC_AMP_OFF)
#define GS2_VREG_RXTX_MAS_ISET_OFF 7
#define GS2_VREG_RXTX_MAS_ISET_60U (0 << GS2_VREG_RXTX_MAS_ISET_OFF)
#define GS2_VREG_RXTX_MAS_ISET_80U (1 << GS2_VREG_RXTX_MAS_ISET_OFF)
#define GS2_VREG_RXTX_MAS_ISET_100U (2 << GS2_VREG_RXTX_MAS_ISET_OFF)
#define GS2_VREG_RXTX_MAS_ISET_120U (3 << GS2_VREG_RXTX_MAS_ISET_OFF)
#define GS2_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
#define GS2_RSVD_6_0_OFF 0
#define GS2_RSVD_6_0_LEN 7
#define GS2_RSVD_6_0_MASK (((1 << GS2_RSVD_6_0_LEN) - 1) << \
GS2_RSVD_6_0_OFF)
#define COMPHY_GEN3_SET2 0x3f
#define GEN3_SET2_ADDR(unit) (COMPHY_GEN3_SET2 * PHY_SHFT(unit))
#define G3_TX_SSC_AMP_OFF 9
#define G3_TX_SSC_AMP_LEN 7
#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
G2_TX_SSC_AMP_OFF)
#define G3_VREG_RXTX_MAS_ISET_OFF 7
#define G3_VREG_RXTX_MAS_ISET_60U (0 << G3_VREG_RXTX_MAS_ISET_OFF)
#define G3_VREG_RXTX_MAS_ISET_80U (1 << G3_VREG_RXTX_MAS_ISET_OFF)
#define G3_VREG_RXTX_MAS_ISET_100U (2 << G3_VREG_RXTX_MAS_ISET_OFF)
#define G3_VREG_RXTX_MAS_ISET_120U (3 << G3_VREG_RXTX_MAS_ISET_OFF)
#define G3_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
#define RSVD_PH03FH_6_0_OFF 0
#define RSVD_PH03FH_6_0_LEN 7
#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
RSVD_PH03FH_6_0_OFF)
#define COMPHY_UNIT_CTRL 0x48
#define UNIT_CTRL_ADDR(unit) (COMPHY_UNIT_CTRL * PHY_SHFT(unit))
@ -139,8 +135,8 @@ enum {
#define SEL_BITS_PCIE_FORCE BIT(15)
#define COMPHY_GEN2_SET3 0x112
#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF
#define GS3_FFE_CAP_SEL_MASK 0xF
#define GS3_FFE_CAP_SEL_VALUE 0xF
#define COMPHY_LANE_CFG0 0x180
#define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0 * PHY_SHFT(unit))